From: sweir ([email protected])
Date: Mon Mar 13 2000 - 23:55:11 PST
SSC synthesizers modulate the clock output frequency at a fairly low rate
in order to spread the frequency spectra of the clock. Since the EMI
energy that is constant is now spread over a wider band, the peak level
falls. This can buy several db improvement.
The PLL must stably track the bandwidth of the SSC clock source without
gaining or losing more phase than allowed for in the timing budget. Be
careful if the PLL uses a phase-frequency detector, as these devices have a
gain dead-band at zero error that causes phase jitter. A typical fix is to
bias the error amplifier with a little DC, so that they do not quite get to
zero error. However, when you use an SSC, the loop gets pushed around a
little, and depending on the coefficients could push the part back into the
ICS( Cypress ) among others build these things.
At 03:09 PM 3/14/00 +0800, you wrote:
>What is a Spread Spectrum Clock synthesizer and why it is used in PC
>motherboards? What are the limitations when chosing a PLL for the Registered
>DIMM if you need to support SSC? Do you know of any such chips?
>With best regards,
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