Re: [SI-LIST] : Fast edges with limited plane capacitance

From: Vinu Arumugham ([email protected])
Date: Fri Mar 17 2000 - 11:07:12 PST

• Next message: Muranyi, Arpad: "RE: [SI-LIST] : Bad IBIS models!"
• Previous message: Doug McKean: "Re: [SI-LIST] : Fast edges with limited plane capacitance"
• In reply to: Larry Smith: "Re: [SI-LIST] : Fast edges with limited plane capacitance"
• Next in thread: Ron Miller: "Re: [SI-LIST] : Fast edges with limited plane capacitance"

Larry Smith wrote:

>
>
> To directly answer Mark's questions, with the same amount of noise
> stimulation, there will be much more noise between the 40 mil power
> planes than between the 4 mil planes, in fact 10X. The reason is
> because of the increased impedance.
>

Doesn't increased power distribution impedance equate to slower logic transition times? If so, the amount of noise stimulation is not the same. If the design's timing margin allows for slower edge
rates, would 40 mil planes not be better than 4 mil planes?

**** To unsubscribe from si-list or si-list-digest: send e-mail to [email protected]. In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
****

• Next message: Muranyi, Arpad: "RE: [SI-LIST] : Bad IBIS models!"
• Previous message: Doug McKean: "Re: [SI-LIST] : Fast edges with limited plane capacitance"
• In reply to: Larry Smith: "Re: [SI-LIST] : Fast edges with limited plane capacitance"
• Next in thread: Ron Miller: "Re: [SI-LIST] : Fast edges with limited plane capacitance"

This archive was generated by hypermail 2b29 : Thu Apr 20 2000 - 11:35:42 PDT