Re: [SI-LIST] : PWR/GND grid effect on EMI in 2-layer board

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From: Lawrence Butcher (Lawrence.Butcher@eng.sun.com)
Date: Tue Apr 04 2000 - 20:04:13 PDT


I helped on a 2-layer board in a plastic box project. It had horizontal
Power AND Ground traces alternating on one side, and vertical Power AND
Ground traces alternating on the other.

At each ground-to-ground and power-to-power crossing, there was a via. As
I recall, we tried to have about 3 signal traces between an adjacent pair
of Power and Ground signals on each side.

This made an odd inter-woven power-ground fabric. The signals were woven
in there too. I felt that a vertical or horizintal return current would
be able to find a nearby supply wire to follow. Plus the current could
jump directions if the signal wire jumped to the other side.

There was a ceramic cap for every chip power pin, at the pin. Of course
there were caps spread around too.

When we did this, all the vias were killing us. They made routing
difficult, so we tweeked them so they wouldn't make bad neck-downs
by all being in a horizontal or vertical line. But more important
to us was the fear of increased cost! It turned out that the PC
board manufacturer wasn't counting holes at all.

Passed EMI. I bet the fact that the processor clock was running in the
low MHz's helped.

If I were trying this stunt again, I might put resistors in series close
to every driver on the board. That way I could SQUEEZE the signals to all
be as slow as possible while still meeting setup requirements.

I would also put important signals, like clocks and bus qualifiers, between
their own pair of ground wires the entire signal length, if possible.

A fun combination of new and old ideas. Hope this is helpful.

L

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