RE: [SI-LIST] : Input switching threshold & CPCI

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From: Abe Riazi (ariazi@anigma.com)
Date: Wed Jan 05 2000 - 10:27:01 PST


     Hi Andy:

    I have seen the 0.8, 2.0 V threshold problem in models that the
vendor had clearly indicated for PCI Bus simulation at 33 MHz/66MHz, 3.3
V signaling. However, the example that I used in my post belonged to a
model obtained from the internet. I was led to think that this model
is suitable for 3.3 signaling from the following section of the model:

   Notes] The following information corresponds to the 3.3 volt
                80960RN processor in the 540 Lead PLGA package.

   However, it is quite possible that this particular example should be
regarded as a 5V compatible 3.3 V model as you had mentioned.

   Regards,

  Abe

     

>----------
>From: Ingraham, Andrew[SMTP:Andrew.Ingraham@COMPAQ.com]
>Sent: Wednesday, January 05, 2000 6:18 AM
>To: 'si-list@silab.eng.sun.com'
>Subject: RE: [SI-LIST] : Input switching threshold & CPCI
>
>>Some behavioral models contain the 0.8, 2.0 V
>>thresholds when inapplicable. A good example is the case of an IBIS
>>model designed for 3.3 V PCI simulation. I have attached below the
>>section of such example which includes the threshold voltages:
>...
>
>I have seen plenty of dumb errors exactly like this in behavioral models.
>Never trust 'em.
>
>However, are you certain this model is for a part with 3.3V signaling
>levels? It's possible that this part is designed for "5V" switching levels
>but is powered by 3.3V (has 5V-compatible 3.3V outputs and 5V-tolerant
>inputs). The "VCC5REF" node is suspicious ... what would this be for in a
>3.3V PCI signaling environment?
>
>Regards,
>Andy
>
>
>
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