Re: [SI-LIST] : PWR/GND grid effect on EMI

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From: jrbarnes@lexmark.com
Date: Wed Apr 05 2000 - 08:39:45 PDT


>I'm relaying out a pcb for one of my customers. The goal is to reduce the cost
>by going from 4-layer (internal PWR and GND planes) bd. down to 2-layers. One
>of the major concerns is increased EMI.
>One of the ideas that was brought up to minimize EMI is to have a "grid" of
>horizontal PWR traces spaced around 2cm from each other on top side and
>vertical GND traces spaced 2cm on the opposite side. In addition, the board
>would have a GND ring around the perimeter on both sides that would be stiched
>with vias. Every point of intersection of these PWR and GND lines will have a
>.01uF and .1uF bypass cap.
>Since I haven't heard about this approach, your input would be appreciated.

Ilya,
You would do much better to tightly grid both power and ground, by putting:
* Horizontal PWR and GND traces topside, next to each other if possible.
* Vertical PWR and GND traces bottomside, ditto.
* Additional GND traces anywhere you can sneak them in, of whatever width will
fit.
* Vias connecting the topside and bottomside PWR traces wherever they cross, as
close as possible to the power
   pins of the IC's and connectors.
* Vias connecting the topside and bottomside GND traces wherever they cross, as
close as possible to the ground
   pins of the IC's and connectors.

I also like to put a ground ring around the board on each layer, and tie these
ground rings together with vias about every 1/2 inch (1.2cm), irregularly
spaced. This style of gridding will give you low inductance in both PWR and
GND. For any direction of current flow within a grid you have multiple paths,
widely spaced so their mutual inductance is low. Therefore the effective
partial inductance between any two points is the partial inductance of any one
path divided by the number of parallel paths between the points. For power
going out to a device, it can return by a parallel ground path which has high
mutual inductance and therefore low overall loop inductance/impedance. You do
lose much of the capacitance between power and ground planes that you would have
on a multilayer board, but for a four-layer FR-4 board that amounts to only
about 100pF/square inch (15 pf/square cm).

After gridding, an overall view of the board might look like (V=via, P=power
trace, G=ground trace):

 overall grids = ground grid + power grid
+----------------------+ +----------------------+ +----------------------+
!VGGVGVGGGGVGGGGVGGGGGV! !VGGVGVGGGGVGGGGVGGGGGV! ! !
!GVPGPGVPPPGVPPPGVPPPVG! !G G G G G G! ! VPPPPVPPPPVPPPPVPPPV !
!GP G GP GP GP PG! !G G G G G G! ! P P P P P !
!GP G GP GP GP PG! !G G G G G G! ! P P P P P !
!GP G GP GP GP PG! !G G G G G G! ! P P P P P !
!VGGVGVGGVGVGGGGVGGGGGV! !VGGVGVGGVGVGGGGVGGGGGV! ! P P P P P !
!GVPPPGVPGPGVPPPGVPPPVG! !G G G G G G! ! VPPPPVPPPPVPPPPVPPPV !
!GP GP G GP GP PG! !G G G G G G! ! P P P P P !
!GP GP G VGGGGVP PG! !G G G VGGGGV G! ! P P P P P !
!GP GP G GP GP PG! !G G G G G G! ! P P P P P !
!VGGGGVGGVGVGGGGVGGGGGV! !VGGGGVGGVGVGGGGVGGGGGV! ! P P P P P !
!GVPPPGVPPPGVPPPGVPPPVG! !G G G G G! ! VPPPPVPPPPVPPPPVPPPV !
!GP GP GP GP PG! !G G G G G! ! P P P P P !
!GP VGGGGVP GP PG! !G VGGGGV G G! ! P P P P P !
!GP GP GP GP PG! !G G G G G! ! P P P P P !
!GVPPPGVPPPGVPPPGVPPPVG! !G G G G G! ! VPPPPVPPPPVPPPPVPPPV !
!VGGGGVGGGGVGGGGVGGGGGV! !VGGGGVGGGGVGGGGVGGGGGV! ! !
+----------------------+ +----------------------+ +----------------------+

 topside traces = ground traces + power traces
+----------------------+ +----------------------+ +----------------------+
!VGGGGVGGGGVGGGGVGGGGGV! !VGGGGVGGGGVGGGGVGGGGGV! ! !
!GVPPPPVPPPPVPPPPVPPPVG! !G G! ! VPPPPVPPPPVPPPPVPPPV !
!G G! !G G! ! !
!G G! !G G! ! !
!G G! !G G! ! !
!VGGGGVGGGGVGGGGVGGGGGV! !VGGGGVGGGGVGGGGVGGGGGV! ! !
!GVPPPPVPPPPVPPPPVPPPVG! !G G! ! VPPPPVPPPPVPPPPVPPPV !
!G G! !G G! ! !
!G VGGGGV G! !G VGGGGV G! ! !
!G G! !G G! ! !
!VGGGGVGGGGVGGGGVGGGGGV! !VGGGGVGGGGVGGGGVGGGGGV! ! !
!GVPPPPVPPPPVPPPPVPPPVG! !G G! ! VPPPPVPPPPVPPPPVPPPV !
!G G! !G G! ! !
!G VGGGGV G! !G VGGGGV G! ! !
!G G! !G G! ! !
!GVPPPPVPPPPVPPPPVPPPVG! !G G! ! VPPPPVPPPPVPPPPVPPPV !
!VGGGGVGGGGVGGGGVGGGGGV! !VGGGGVGGGGVGGGGVGGGGGV! ! !
+----------------------+ +----------------------+ +----------------------+

 bottomside traces = ground traces + power traces
+----------------------+ +----------------------+ +----------------------+
!VGGVGVGGGGVGGGGVGGGGGV! !VGGVGVGGGGVGGGGVGGGGGV! ! !
!GV G GV GV GV VG! !G G G G G G! ! V V V V V !
!GP G GP GP GP PG! !G G G G G G! ! P P P P P !
!GP G GP GP GP PG! !G G G G G G! ! P P P P P !
!GP G GP GP GP PG! !G G G G G G! ! P P P P P !
!VP V VP V VP VP PV! !V V V V V V V! ! P P P P P !
!GV GV G GV GV VG! !G G G G G G! ! V V V V V !
!GP GP G GP GP PG! !G G G G G G! ! P P P P P !
!GP GP G GP GP PG! !G G G G G G! ! P P P P P !
!GP GP G GP GP PG! !G G G G G G! ! P P P P P !
!VP VP V VP VP PV! !V V V V V V! ! P P P P P !
!GV GV GV GV VG! !G G G G G! ! V V V V V !
!GP GP GP GP PG! !G G G G G! ! P P P P P !
!GP GP GP GP PG! !G G G G G! ! P P P P P !
!GP GP GP GP PG! !G G G G G! ! P P P P P !
!GV GV GV GV VG! !G G G G G! ! V V V V V !
!VGGGGVGGGGVGGGGVGGGGGV! !VGGGGVGGGGVGGGGVGGGGGV! ! !
+----------------------+ +----------------------+ +----------------------+

Try to have 2-to-4 traces going to each power/ground pin on the board. If you
must use a single trace to connect an IC/connector/capacitor pin to the
appropriate grid, make it short and fat-- less than a 3:1 or 5:1 length-to-width
ratio,
and try to terminate the other end in a via to take advantage of the horizontal
and vertical current paths. You will almost always be better off having the
power/ground traces squirming across the board, going directly between
IC/connector/capacitor pins, than having the power/ground traces straight with
stubs coming off them.

Put the bypass capacitors for an IC as close as possible to its power pins, with
the other end connected to a ground trace that goes as directly as possible to
the associated ground pin(s). If an IC has a phase-locked loop (PLL), for
example, it will almost always have a Vccpll and a GNDpll pin associated with
it. Put the bypass capacitor(s) for the PLL across these pins, and the bypass
capacitors for the regular Vcc and GND pins between those pins. This placement
takes advantage of the more extensive gridding, and therefore lower
inductance/impedance that we usually achieve on ground versus power. I like to
have a bypass capacitor for each power pin, or closely grouped set of power
pins, on an IC. If power pins are next to each other, or separated by only one
other pin, I let them share a bypass capacitor. Otherwise each power pin gets
its own bypass capacitor. If you put two bypass capacitors on a pin their
values should be in a 100:1 ratio-- a 100nF capacitor paralleled by a 1nF
capacitor, or a 10nF capacitor paralleled by a 100pF capacitor. This keeps
the impedance from skyrocketing at a frequency where the inductance of the large
capacitor resonates with the capacitance of the small capacitor. If you are
using Surface Mount Technology (SMT)
ceramic capacitors, their self-resonant frequency (SRF) is so high that you will
probably need two bypass capacitors only for oscillators and PLL's. See my post
from last week, where I measured 80+ types/values of ceramic and tantalum
capacitors on a Network/Spectrum Analyzer. SMT capacitors have incredibly
better high-frequency performance than pin-through-hole capacitors.

You will also probably need to put some bulk capacitors on the board. At least
one should be close to the power-entry point. If the board is large, you will
be wise to also put bulk capacitors:
* At the farthest point on the board from the power input.
* At the power pins of connectors for peripheral devices or adapter boards.
* Close to any components that are particular "power hogs".

We have used this style of gridding, with grids about 1/2" by 1/2" (1.2cm x
1.2cm), on network adapter cards with clock speeds up to 45MHz. We do use
Spread Spectrum Clock Generators (SSCG's) wherever we can, to meet FCC/CISPR
Radiated Emissions limits on these two-sided cards.

                                         John Barnes Advisory Engineer
                                         Lexmark International
                                         author of Electronic System Design:
                                           Interference and Noise Control
Techniques

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