[SI-LIST] : Catching the Corners: chain of synchronizing registers

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From: Shayle Hirschman ([email protected])
Date: Sat Mar 18 2000 - 07:31:03 PST

Dr. Johnson writes:

"Sometimes we use a chain of synchronizing registers when sampling and
asynchronous signal. In a chain of synchronizers, things work a little
differently. The metastable resolution delay at the output of the first
 flip-flop in the chain causes a problem ONLY if it hits RIGHT ON
TOP of the actual metastable sampling window for the second flip-
flop. Since this second window is extremely narrow (much narrower
than the worst-case published specifications for setup and hold times),
your MTBF calculations benefit not only from the amount of resolution
time T made available by each stage, but also from the width of the
resolution windows. In mathematical terms, the output transition from th
 first stage has to hit between T and T+dT, where dT is the window width
of the second stage, in order to cause an error. This effect renders a
two-stage (or three-stage) sampler running at rate R almost as
effective as a single-stage sampler using a slower clock of R/2 (or

My question is regarding how to determine the clock frequency with two or
more successive flip-flops.

By just using one, the clock period is the traditional tCO + tSU +
selected from a statistical table based upon the acceptable mean time
between failures.

Now, with two or more synchronizing FF's, as you state, the clock frequency
is greatly reduced. I assume it cannot be reduced all the way to the point
of no additional time for metastate resolution.

As usual, given the minimum required mean time between failures traded off
against the minimum design frequency, how is this increased frequency now
calculated using two or more FF's?

Thank you in advance.


Shayle I. Hirschman, Senior Engineer
Managing Director
Digital Design Solutions
[email protected]
Phone 901/759-1802 Fax 901/759-2324

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