From: D. C. Sessions (firstname.lastname@example.org)
Date: Tue Mar 21 2000 - 12:53:40 PST
Weston Beal wrote:
> Dear IC experts,
> I've been working a problem that might involve the C_comp parameter in an
> IBIS file. In discussion with others, I find some difference of opinion.
> the IBIS spec says that C_comp represents the capacitance on the die. I
> understand this to be the bond pad, clamp diode reverse bias capacitance,
> and final stage transistor channel capacitance. What other effects are
> important contributors to C_comp? I suspect that the bond pad is the
> dominant factor in todays technology. Is that correct? What are typical
> values for the components I've listed?
C_Comp is whatever value most closely approximates the high-frequency
response that an incoming wave 'sees' hitting the IC. Personally, I
prefer deriving it from doing a best-fit optimization matching a cap
to a fully extracted SPICE netlist of the physical part. For most
I/O cells this runs just a bit over 1.0 pf, mostly in the gate/drain
capacitance of the output devices. The other contributors (diffusion
to bulk, pad to substrate) have such high ESR as to be negligible.
Warning: most test groups want to measure input capacitance at 1 MHz,
and this gives dramatically higher values. There's been blood on the
floor in JEDEC meetings over this very difference.
-- D. C. Sessions email@example.com
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