**From:** Ray Anderson (*raymonda@radium.eng.sun.com*)

**Date:** Wed Jan 26 2000 - 10:27:49 PST

**Next message:**Ron Miller: "Re: [SI-LIST] : Decoupling capacitor resonance"**Previous message:**SPI Workshop: "[SI-LIST] : Workshop on Signal Propagation on Interconnects"**Maybe in reply to:**Chris Bobek: "[SI-LIST] : Decoupling capacitor resonance"**Next in thread:**Brent DeWitt: "[SI-LIST] : Another capacitor question"**Reply:**Brent DeWitt: "[SI-LIST] : Another capacitor question"

When designing a low impedance power distribution system, the goal is

to maintain a low impedance (lower than some calculated target impedance)

across a wide bandwidth.

Utilizing the ability to select various values of decoupling capacitance

that will resonate with the mounted inductance of those parts, one can

provide a low impedance over quite a large range.

There are two phenomena that come into play when considering the capacitors

resonance. There is a series resonance (desired) where the impedance of the

bypass capacitor is minimum (actually it bottoms out at the ESR of the part)

which provides a low impedance path from the power plane to the reference

plane at a particular frequency. The second phenomena is caused by the

interaction between bypass capacitors in the form of an 'anti-resonance'

which manifests itself as a high impedance. This is a parallel resonance. It

will be found that the lower the ESR of the involved capacitors is, the

higher the magnitude of this anti-resonance response. Also it will be noted

that it will become higher in magnitude as a function of mounted inductance.

The goal is to design a broadband low impedance profile based on the

superposition of the impedance profiles of the individual capacitors while at

the same time minimizing the effect of any anti-resonance responses. It can

be done, and we use this scheme with great success in our high performance

systems.

This means that if you are going to use multiple low ESR parts to effect a

broadband low-impedance bypassing scheme (which I am advocating), you MUST

make sure you have a low mounted inductance for the parts. The mounting

inductance is primarily dependent on the pad and escape geometry as well as

the associated via lengths and power plane spacing. The inductance is a

function of the loop area of the current path as well as the spreading

inductance of the planar structure. The inductance contributed by the actual

capacitor structure is a relatively small part of the total inductance.

By properly managing the various components of the power distribution system

(voltage regulator module, bulk capacitors, hf decoupling capacitors, vhf

decoupling capacitors and plane stackup) one can indeed develop a power

distribution sytem that exhibits a low impedance from very low fequencies

(10's of Hertz) up to multiple 100's of MHz. With the proper technology this

can be extended to the multi GHz region.

To quickly summarize:

You need to carefully select decap values [ f = 1/(2pisqrt(LC)) ]

You need to make sure you have a low mounted inductance (geometry)

You need to use low ESR parts (dielectric type matters)

You need to pay attention to plane stackup (thickness and model)

You need to know the output Z characteristics of the VRM (model)

You need an accurate, quick simulation of the power distribution system (spice)

A tool has been developed based on this methodology and it will be

commercially available in the not too distant future from a major CAD vendor.

The tool allows the user to efficiently select the necessary decaps, place

them on a power plane and perform simulations to analyze the resulting

performance.

Necessarily this note is limited in scope and detail. A more in depth

description of the methodology and the underlying theory can be found in a

paper presented at EPEP authored by Larry Smith, myself and others here at

Sun Microsystems. The paper is available for download as a PDF file at the

following URL: http://www.qsl.net/wb6tpu/si_documents/docs.html

Ray Anderson

Sun Microsystems

*> Date: Tue, 25 Jan 2000 17:42:02 -0800
*

*> From: Chris Bobek <cbobek@cadence.com>
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*> To: Si-list <si-list@silab.eng.sun.com>
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*> Subject: [SI-LIST] : Decoupling capacitor resonance
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*> X-Received: By mailgate.Cadence.COM as RAA23775 at Tue Jan 25 17:44:40 2000
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*>
*

*> Hi,
*

*>
*

*> There's been a lot of discussion about selecting the right decoupling
*

*> capacitor(s) for an IC. Howard Johnson's philosophy seems to say "pick
*

*> the largest value cap(s) in the smallest smt package that you can
*

*> reliably purchase". I tend to agree with that. However, I have an
*

*> appnote for a PLL (f~=50Mhz) that says to use a 22uF and a 10pF to
*

*> properly decouple the device. Instead, I'm using a 22uF and a 0.1uF in
*

*> the smallest package I'm allowed to procure (0805). FOR THE SAME SIZE
*

*> PACKAGE, should I change the 0.1uF to 10pF? If so, why?
*

*>
*

*> My understanding is that the inductance of the 10pF and 0.1uF is almost
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*> equal (because they are in the same size package). Inductance being
*

*> equal, the larger capacitance is better because it provides a lower
*

*> impedance to ground. Therefore, using a 10pF would not gain us anything
*

*> except an extra part to procure in addition to our ubiquitous 0.1uF's.
*

*>
*

*> Thank you for your help/insight,
*

*>
*

*> Chris
*

*>
*

*>
*

*>
*

*>
*

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**Next message:**Ron Miller: "Re: [SI-LIST] : Decoupling capacitor resonance"**Previous message:**SPI Workshop: "[SI-LIST] : Workshop on Signal Propagation on Interconnects"**Maybe in reply to:**Chris Bobek: "[SI-LIST] : Decoupling capacitor resonance"**Next in thread:**Brent DeWitt: "[SI-LIST] : Another capacitor question"**Reply:**Brent DeWitt: "[SI-LIST] : Another capacitor question"

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