RE: [SI-LIST] : via capacitance

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From: Ron Miller (rmiller@Brocade.COM)
Date: Mon Apr 10 2000 - 13:40:27 PDT


Hi Ritchey]
The capacitance can be as low as what you say, but it can be much worse.

In the microwave business where we are dealing with single layers of
dielectric or a couple
in the case of stripline, vias are typically modeled as inductors, which
they appear to be.

With multilayer PCB the capacitance becomes the dominating factor with the
plate structure
being primarily between the outside of the antipads on power and ground
layers and the pads
attached to the signal via on the unused layers. These unused pads can be
easily removed on a global
asis in Alegro and other layout tools. However, often they are not and the
excess capacitance can cause
impedances to go down to about 35 ohms on a TDR. Also, vias can have
open-stub effect which adds
more capacitance at microwave frequencys.

SO ??

  0.3pf is not the worst case. It is probably the best case if the traces,
vias, pads and antipads
are all done well

Also, it looks like you laid your boards out well.

Ron Miller

> -----Original Message-----
> From: Ritchey Lee
> Sent: Monday, April 10, 2000 9:16 AM
> To: si-list@silab.eng.sun.com
> Subject: Re: [SI-LIST] : via capacitance
>
>
        [Ron Miller]

> I have done many experiments to determine the capacitance value of vias.
> A 13 mil diameter via, 100 mils long has approximately .3 pF of
> capacitance. Your traces will average about 3 pF per inch of
> length. The small value of the via capacitance will not be detectable at
> edge rates slower than 100 pSEc.
>
> Sunil Kumar wrote:
>
> > Dear all SI experts.
> >
> > I am using a multilayer board having the following stack-up:
> >
> > LAYER1 TOP LAYER (CONDUCTOR)
> > LAYER2 GND
> > LAYER3 CONDUCTOR
> > LAYER4 CONDUCTOR
> > LAYER5 VCC
> > LAYER6 GND
> > LAYER7 CONDUCTOR
> > LAYER8 CONDUCTOR
> > LAYER9 GND
> > LAYER10 BOTTOM LAYER (CONDUCTOR)
> >
> > A signal trace is going from layer7 to layer8. A through-hole via is
> used.
> > The via is having pads on layers 1,7,8,10. There are antipads on the
> power
> > planes. Is there any formula/tools to calculate the exact capacitance of
> > the via?? How can I measure it in the board??
> >
> > Sunil Kumar
> > Research Engineer
> > C-DOT
> > INDIA
> >
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