Re: Fw: [SI-LIST] : via capacitance

About this list Date view Thread view Subject view Author view

From: brent.dewitt@us.datex-ohmeda.com
Date: Mon Apr 10 2000 - 15:58:22 PDT


I'm glad you said that. That was my initial impression as well and I wondered
what I was missing.

Best regards,

Brent

Ritchey Lee <leeritchey@earthlink.net> on 04/10/2000 10:21:14 AM

Please respond to si-list@silab.eng.sun.com

To: si-list@silab.eng.sun.com
cc: (bcc: Brent Dewitt/US/D-O)

Subject: Re: Fw: [SI-LIST] : via capacitance

A better choice is two signal layers in the middle and two signal layers on each
side, outside the planes.

Lee

Jon Keeble wrote:

> Following advise from this list, for 10 layer boards I prefer the following
> stackup:
>
> LAYER1 TOP LAYER (CONDUCTOR)
> LAYER2 VCC
> LAYER3 GND
> LAYER4 CONDUCTOR
> LAYER5 CONDUCTOR
> LAYER6 CONDUCTOR
> LAYER7 CONDUCTOR
> LAYER8 VCC
> LAYER9 GND
> LAYER10 BOTTOM LAYER (CONDUCTOR)
>
> This puts the power planes close together (maxim distributed capacitance)
> and close to the surface (minimum impedance between silicon and power
> distribution).
>
> I used to think that it was useful to minimise the inductance between the
> bypass caps and the power planes. However, each capacitor has a low
> impedance over a range of frequencies centered on its self resonance, and an
> extra nH or two simply moves this range down. Recent work revealed in this
> list shows that a number of different, close-spaced values can deliver a low
> impedance over the full spectrum.
>
> I don't think it matters which way round VCC and GND goes.
>
> The middle routing layers can be routed at 0, 30,60,90 degrees to minimise
> crosstalk.
>
> Jon Keeble
>
> >-----Original Message-----
> >From: Sunil Kumar <sunilb@cdotb.ernet.in>
> >To: si-list@silab.eng.sun.com <si-list@silab.eng.sun.com>
> >Date: Saturday, April 01, 2000 11:25 AM
> >Subject: [SI-LIST] : via capacitance
> >
> >
> >>
> >>Dear all SI experts.
> >>
> >>I am using a multilayer board having the following stack-up:
> >>
> >>LAYER1 TOP LAYER (CONDUCTOR)
> >>LAYER2 GND
> >>LAYER3 CONDUCTOR
> >>LAYER4 CONDUCTOR
> >>LAYER5 VCC
> >>LAYER6 GND
> >>LAYER7 CONDUCTOR
> >>LAYER8 CONDUCTOR
> >>LAYER9 GND
> >>LAYER10 BOTTOM LAYER (CONDUCTOR)
> >>
> >>A signal trace is going from layer7 to layer8. A through-hole via is
> >>used.
> >>The via is having pads on layers 1,7,8,10. There are antipads on the
> >>power
> >>planes. Is there any formula/tools to calculate the exact capacitance of
> >>the via?? How can I measure it in the board??
> >>
> >>
> >>Sunil Kumar
> >>Research Engineer
> >>C-DOT
> >>INDIA
> >>
> >>
> >>**** To unsubscribe from si-list or si-list-digest: send e-mail to
> >>majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE
> >>si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
> >>si-list archives are accessible at http://www.qsl.net/wb6tpu
> >>****
> >
>
> **** To unsubscribe from si-list or si-list-digest: send e-mail to
majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list or
UNSUBSCRIBE si-list-digest, for more help, put HELP.
> si-list archives are accessible at http://www.qsl.net/wb6tpu
> ****

**** To unsubscribe from si-list or si-list-digest: send e-mail to
majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list or
UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
****

**** To unsubscribe from si-list or si-list-digest: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
****


About this list Date view Thread view Subject view Author view

This archive was generated by hypermail 2b29 : Thu Apr 20 2000 - 11:36:07 PDT