From: Lawrence Butcher (Lawrence.Butcher@eng.sun.com)
Date: Fri Mar 17 2000 - 12:59:06 PST
A question about 1) S-S-P-G-S-S vs 2) S-P-S-S-G-S stackup.
I have often wondered whether it would be a good idea to use
2) above, but to use all available space on the inner S layers
as additional P and G layers.
Assuming that a large fraction of the inner layers were avaialable,
and that the board could be swiss-cheesed with vias, the stackup
would look like S-P-G-P-G-S.
Unfortunately there is large spacing between the internal power and
Is this a half-way step which might behave well at low frequencies
due to buried traces, and well at high frequencies due to the
higher buried capacitance?
Even in the case of 1), should we be using all available unused
routing layers as additional buried capacitance?
This could be a "simple" post-routing step in the PCB design process.
It could be applied to boards with any stackup.
It might make it fun to try to run constant-impedance traces around
the board, though. We would have to keep our eyes on changing
geometries and complicated return current paths.
**** To unsubscribe from si-list or si-list-digest: send e-mail to firstname.lastname@example.org. In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
This archive was generated by hypermail 2b29 : Thu Apr 20 2000 - 11:35:44 PDT