RE: [SI-LIST] : Bad IBIS models!

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From: Weston Beal (weston_beal@mentorg.com)
Date: Wed Mar 15 2000 - 15:18:42 PST


Stephen,

This is a great list! Please add my pet peeve, TIMING REFERENCE LOAD.
Vmeas, Vref, Rref, Cref must be present and equal to what is used to measure
timing stated on the device data sheet.

Also, curve values should be reasonable. A clamp diode doesn't pass
12.3487E+23 A, but I see this in IBIS file all the time. Details like this
cause me to doubt the integrity of the whole file.

Regards,
Weston

-----Original Message-----
From: owner-si-list@silab.eng.sun.com
[mailto:owner-si-list@silab.eng.sun.com]On Behalf Of Stephen Nolan
Sent: Wednesday, March 15, 2000 2:36 PM
To: si-list@silab.eng.sun.com
Subject: Re: [SI-LIST] : Bad IBIS models!

SI-List,

What, exactly would be the QC steps that you would like to see component
vendors
ensure that their models pass, prior to release?

What I've gleaned so far:

- Validate to IBISCHK3 and document exceptions to warnings.

- Validate all curves with a visual graphing for discontinuity, or other
visually obvious errors.

- Validate that the VI curves pass through origin.

- Verify that a full pin map exists and is accurate against datasheet.

- Verify that all models exist.

- Validate accuracy of package parastics.

- Validate accuracy of dV/dt. Use 50 ohm load or datasheet load?

- Include and validate accuracy of C_comp, including min and max.

- Include 4 VT curves minimum. Use 50 ohm load or datasheet load?

- Include accurate Min, Typ, Max data, derived from a setup that has full
variation across PVT.

What else? Thanks.

--
Regards,
Stephen M. Nolan

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