Re: [SI-LIST] : Reflections on clock line

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From: Tadashi ARAI (arap@paso.fujitsu.co.jp)
Date: Thu Apr 06 2000 - 04:37:39 PDT


Howdy Tham,

It often was occured such a reflection problem on daisy-chain
connection.

Use "H" topology to solve it.

Divide clock line with T junction at exact center of 8 loads, after that
devide again at exact center of each 4 loads, and after that devide at
center of each 2. The point is that each "branch" must be the same
length.

Regards,
//// /// // / / / / / / / / / /
Tadashi Arai//Platform Developing Dept.,Desktop Prd Div. Fujitsu Limited
arap@paso.fujitsu.co.jp TEL:+81-42-370-7624 Inagi-shi, Tokyo, Japan
/ / / / / / / / / / / // ///
On Wed, 05 Apr 2000 11:15:04 -0700
Mail from tham@uti2000.co.jp described as below:

> Hi,
>
> I have a 20in long 50MHz clock line which connected to 8 loads(5.5pF per
> load). (Vcc=3.3)
> I used daisy-chain to connect all loads but the waveform of the nearest
> receiver (respective to the driver) only swing between 1V and 2V. The
> waveform of the furthest receiver overshoot above 4V.
> I think reflection is the main reason and I had put an end termination
> but
> there is no improvement for the nearest receiver waveform.
> Anybody have any ideal to solve this problem?
> I appreciate any advice or suggestions.
>
> Thanks.
>
> Regards,
> KT.THAM
>
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