Re: [SI-LIST] : montonic signals at SDRAM-, SSRAM- and FEPROM-adress inputs

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From: Scott McMorrow (scott@vasthorizons.com)
Date: Sat Feb 12 2000 - 01:08:35 PST


Dirk and all,

Non-monotonic waveforms in the threshold region of any device
are problematic. These are not usually specificed and can cause
undesired behavior. As device inputs become faster they tend
to be even more sensitive to noise in the switching region.

For address inputs, specifically, if there is plenty of timing margin,
(and by plenty I mean 5 ns) then there is not an issue. Most memory
controllers use CS to hold back address inputs until two clock
cycles after issuing an address just for this reason.

One should be extremely careful about non-monotonic and slow
rising and falling edge rates at the address inputs of SDRAM devices
if you are within a few ns of the setup window. You might get a nasty
surprise in high memory error rates.

regards,

scott

--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com

Netzler Dirk wrote:

> Hello All, > > every time I have to design memory buses I wonder wether signals at adress > inputs > of synchronous memory chips (SDRAM, SSRAM) ) must have monotonic edges or > not. > If yes, can anybody give me an explanation for that ? > > And what's about FEPROMs ? Okay, the control signals (e.g. WE,OE) need to be > monotonic. > But what's about the adress inputs ? Should they be monotonic, too ? I don't > find reasons for that. > > What are your experiences ? > > Best regards > > Dirk Netzler > Siemens AG > > **** To unsubscribe from si-list or si-list-digest: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. > si-list archives are accessible at http://www.qsl.net/wb6tpu > ****

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