From: Jeremy Plunkett (firstname.lastname@example.org)
Date: Mon Feb 28 2000 - 15:44:44 PST
2nd try, optimized for readability. Sorry for the mailbox
from a regular engineer, NOT an HR dept or headhunter...
(they did help w/ the writing, though)
ServerWorks, the leading independent supplier of
high-performance core logic for IntelR-based servers, is a
fast-growing pre-IPO hardware design company with openings
for signal integrity engineers, iocell designers, system
design engineers, and pcb layout engineers.
We have immediate openings for experienced signal integrity
engineers. Our signal integrity group provides support for
all design activities within Serverworks, from system
architecture to board layout.
Work with ASIC Design Engineers, System Engineers, and PCB
Layout Engineers to design products based on the latest
generation Intel microprocessors, memory and I/O
technologies. Design and perform analog simulations of
system level interconnects for next generation Server
platforms. Perform system level pre and post layout signal
integrity analyses for high speed signals including timing,
cross talk, ground bounce, and power quality. Support
next-generation ASICs with IBIS modeling, characterizing and
qualifying device packages/pinouts, lab measurements,
documenting/analyzing results. Assist in
developing/refining simulation tools and methodologies.
Support the company with expertise in electrical design and
Requires familiarity with high performance systems and
optimizing topology layouts for high speed designs,
analyzing and selecting IC technology for data, clock, and
I/O busses. Excellent working knowledge of signal
integrity and high-speed design issues in PCBs. Working
experience with XTK & HSPICE highly desired. Experience
using field solvers for transmission line design and working
with HSPICE and IBIS models a plus. BSEE or MSEE along with
2+ years needed.
EE background required, consideration will be given to any
level of experience from junior to senior level.
For IMMEDIATE RESULTS, please send your resume by email,
FAX, or post to:
V.P. Technical Marketing
2251 Lawson Ln
Santa Clara, Ca. 95054
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