RE: [SI-LIST] : Fast edge termination choice

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From: Kowal, Keith (kowal@cabletron.com)
Date: Fri Feb 25 2000 - 13:04:53 PST


I would suggest using series resistor termination, one resistor
on each end. The two resistors should be tied to a voltage
source/(plane, if permitting) and well decoupled . This works
very well for BTL/GTL type drivers.

 If you are concerned about power dissipation
and resistor count you can cut the R count by half
Also avoid resistor networks at that speed...if your
Zo of the etch is 50 ohms or so then try termination
of R=40ohms on each end / simulate it - we have
done something like this with speeds up to 170mhz
or so....

Keith Kowal
978-684-1574

> -----Original Message-----
> From: Shayle Hirschman [SMTP:shayle@mho.net]
> Sent: Friday, February 25, 2000 9:34 AM
> To: si-list@silab.eng.sun.com
> Subject: [SI-LIST] : Fast edge termination choice
>
> SI experts:
>
> I am interested in making a decision between series source termination and
> parallel termination (probably something like 100 ohms to vcc and 100 ohms
> to gnd) at the destination of a point to point route.
>
> I want to use the fast slew rate option of the FPGA as the clock is 150
> MHz
> and there isn't much timing budget from chip to chip.
>
> Does series source termination defeat the purpose of selecting the fast
> slew rate option? Will it slow the edge transition time down, or will the
> signal still transition and travel as fast as if there was no termination,
> but simply be divided (thereby depending on the reflection at the
> destination)?
>
> I suspect the latter, except that I've heard people say that series source
> termination reduces EMI by slowing the edges down. Could it be that it
> reduces EMI, not by slowing the edges down, but rather just simply because
> it terminates? And that, therefore, as far as EMI goes, parallel
> termination would have a similar EMI result?
>
> If the edge rate does not diminish by using series source termination,
> then
> I would prefer that method since it uses only one resistor and has no DC
> bias current as does parallel termination.
>
> Any suggestions?
>
> Thanks in advance.
>
> Shayle
>
>
> *************************************************************
> Shayle I. Hirschman, Senior Engineer
> Managing Director
> Digital Design Solutions
> http://www.digital-designs.com
> shayle@mho.net
> Phone 901/759-1802 Fax 901/759-2324
>
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