Re: [SI-LIST] : Stack up

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From: Doug McKean (dmckean@corp.auspex.com)
Date: Mon Feb 21 2000 - 15:51:40 PST


Personally, Iulian, I'd swap your 1.8V and
GND layers. Then, make sure all signals
layers are referenced to a Gnd layer.
Can't say it's absolutely imperative.

Regards, Doug McKean

Iulian Ungureanu wrote:
>
> Hi
>
> I'm listening to this list for some time now and I would like to ask your
> opinion on a stack-up I'm working on.
> It is a board with 4x64 pairs of LVDS signals, 77.76 MHz clock, high
> speed(777.6 Hb/s).
>
> I came up with a 14 layers that looks like that:
>
> Signal top fanout, some analog power
> 1.8V
> Gnd
> Sig1 LVDS
> Sig2 LVDS
> Gnd
> Sig3 LVDS
> Sig4 LVDS
> Gnd
> Sig5 LVDS
> Sig6 PECL clocks
> 3.3V
> Gnd
> Signal bottom fanout
>
> I'll be using 1.6 mil core for my high speed cap.
> I would gladly use less layers, but I'm being forced by the HS3
> connectors.
>
> I would really appreciate your opinion.
>
> Thanks,
>
> Iulian Ungureanu
> PCB Designer
> PMC-Sierra,Inc.
> Iulian_Ungureanu@pmc-sierra.com
> http://www.pmc-sierra.com
> Voice:(604)415-6053 Ext.2586
> Fax:(604)415-6206
>
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