RE: [SI-LIST] : PLL clock buffer chips and the feedback loop

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From: Peters, Stephen (stephen.peters@intel.com)
Date: Thu Apr 06 2000 - 14:16:21 PDT


Hi andy, you wrote:

<snip>

>Anyways, a data sheet for the IDT74FCT807CT tells me that the max skew
>between outputs is 250 ps - nearly the same as the output skew of the TI
>CDCF2509 PLL part! I just wish it had twelve outputs instead of ten,
although I'm sure I can find something that'll work.

I've been following this thread off and on, mostly becasuse I'm involved
doing the same exact type of design -- distributing clocks to an FPGA and
banks of SRAM using RoboClock. If your clock driver is short of outputs,
and your FPGA is from the Xilinx Virtex family, one option is to drive the
SRAMS clocks from the FPGA using a DLL clock mirror. The technique is
described in the Xilinx app notes. Depending on the number of outputs
required, I've acheived 350ps of skew between the clock at the FPGA input
and the clock(s) at the SRAMS.

Just a thought.

   Regards,
   Stephen Peters
   Intel Corp.

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