RE: [SI-LIST] : Number of GND/Power pins in a connector ?

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From: Gaines, William (WILLIAM.GAINES@Aerojet.com)
Date: Fri Mar 24 2000 - 08:28:44 PST


The usual reason to use male pins on the daughter card is because it is much
easier to protect the male pins with a shroud, or connector placement on the
pwb. Having male pins on the motherboard makes them very susceptible to
damage during assembly and handling.

Bill Gaines
Sr. Engineer, Electronic Packaging, Aerojet, Azusa
626-812-2199 m-f 7-3:30 626-969-5772 fax
william.gaines@aerojet.com 626-849-2324 pager

> ----------
> From: Lum Wee Mei[SMTP:lweemei@dso.org.sg]
> Reply To: si-list@silab.eng.sun.com
> Sent: Thursday, March 23, 2000 3:18 PM
> To: si-list@silab.eng.sun.com
> Subject: Re: [SI-LIST] : Number of GND/Power pins in a connector ?
>
> Since we are in this question, I would like to add one :
>
> Is there a preferrence to use female connector on a board? I was told that
> male connector is not prefer because the pins may acts as antenna loops
> when the board is left alone.
>
> Can someone enlighten me on this subject?
> Thanks.
>
>
>
> Scott McMorrow wrote:
>
> > Stuart,
> >
> > "It depends" is the correct answer.
> >
> > The best way to size the number of ground and power pins in
> > a connector is to simulate the regions on either side of the
> > connector. The connector model should be fully coupled for
> > all pins including power and ground. You should grid the ground
> > and power planes around the connector edge and within the
> > grid include the decoupling capacitors. A connector swath
> > should be simulated with data transmitted in both directions
> > (if bidirectional) and driven by worst case driver edge rates into
> > transmission lines which are referenced to the non-ideal power
> > and ground grid. Multiple data patterns should be simulated
> > for worst case pattern sensitivity.
> >
> > These sorts of simulations will answer several questions:
> >
> > How much data skew and jitter is caused by connector crosstalk,
> > and return path effects for each ground/power pattern?
> >
> > What happens when a signal is referenced to a ground plane
> > on one side of the connector and to a power plane on the
> > other side?
> >
> > How much noise is induced by data switching into the ground and
> > power grids on either side of the connector?
> >
> > What is the worst case instantaneous voltage differential
> > across the ground pins on either side of the connector?
> >
> > What is the worst case instantaneous voltage differential
> > across the power pins on either side of the connector?
> >
> > And for bonus points:
> >
> > If you have accurate modeling of the power switching currents of
> > the devices on either side of the connector, you can simulate the
> > worst case connector and plane noise due to power transients
> > and data switching transients.
> >
> > Depending on the edge rate and the quality of the connector you
> > may find that although you need few power and ground pins to
> > facilitate clean power delivery, you may need many more power
> > and ground pins to facilited clean signal delivery.
> >
> > regards,
> >
> > scott
> >
> > --
> > Scott McMorrow
> > Principal Engineer
> > SiQual, Signal Quality Engineering
> > 18735 SW Boones Ferry Road
> > Tualatin, OR 97062-3090
> > (503) 885-1231
> > http://www.siqual.com
> >
> > Stuart Adams wrote:
> >
> > > How do I calculate the number of ground and power
> > > pins I need in a board-to-board connector.
> > >
> > > The number of grounds is a function of switching
> > > current and how many signals will switch at the same
> > > time, correct ?
> > >
> > > More grounds is always better but what about power pins ??
> > >
> > > If one or two pins are sufficient to carry the max steady
> > > state current and my board is well bypassed with bulk and
> > > ceramic caps, is there a need for alot more power pins ?
> > >
> > > -- Stuart
> > >
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