Re: [SI-LIST] : Hatch

About this list Date view Thread view Subject view Author view

From: cadpro2k@dacafe.com
Date: Wed Mar 08 2000 - 12:05:15 PST


>Date: Wed, 08 Mar 2000 12:53:37 -0500
>From: "DORIN OPREA" <doprea@newbridge.com>
>Subject: [SI-LIST] : Hatch
>I try to understand the hatch EMC effect on the PCB,
>whether this floating copper required for the copper
>balance is a EMC problem for high speed design
>or not and what will be the limit it start to be one.

Hi Dorin,

I have seen both sides of the fence, without any "real" data either way
to proved the hypothetical question "Does it affect the design". I know
many boards where the fab house has hatched or added copper shapes
(round pads or ovals, etc) to the outer layers to help balance the
copper for plating up the copper, and I've seen a few where the fab
houses has asked to add copper to the internal signal layers for etching
concerns, but I've never seen the data to proved it's detrimental to the
circuit design. I've had one engineer that would allow it, only on the
external layers, but asked to fab shop to hold it back .300" from any
design feature (pads, traces, etc). I'm fairly certain the fab shops
hold it back .100" minimum as a practice, and it's extremely easy for
them to do in their CAM tools, and it tends to help their
manufacturability.

Good luck.

Mitch
Sr PCB Designer
San Diego, CA
_____________________________________________________________
Tired of limited space on Yahoo and Hotmail?
Free 100 Meg email account available at http://www.dacafe.com



**** To unsubscribe from si-list or si-list-digest: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
****


About this list Date view Thread view Subject view Author view

This archive was generated by hypermail 2b29 : Thu Apr 20 2000 - 11:35:29 PDT