Date: Fri Mar 17 2000 - 09:27:42 PST
Jim, Andrew, et al:
The various comments have quite correctly quoted the interrelationship of
permeability and permitivity to assure everyone that Pd (delay/unit length)
really DOES equal (LC)^(1/2). The dependence on the geometry of both L and C
per unit length maintains the same propagation delay per unit length (for
buried traces; i.e., for homogeneous dielectric) at Pd=
(length/c)*(er)^(1/2). The basic equations for total loop inductance and
capacitance per unit length directly confirm this fact.... Or do they?
The answer is, of course, YES. HOWEVER, the implied assumptions of a
homogeneous dielectric, non-varying conductor dimensions and/or dielectric
thickness, and the non-proximity (and therefore parasitic loading) of other
structures and components in todays printed circuit board and chip assemblies
is only partially applicable. If you have a tight delay and/or jitter
specification to meet for proper system performance, you had better know (and
model) these influences on your circuit net.
Because of parasitics, Pd is NOT equal to (LC)^(1/2), but rather
(Leffective*Ceffective)^(1/2). We are all familiar with the added
capacitance and mutual inductance of adjacent traces (to a trace under
analysis). And we all know the added delay of distributed trace capacitance
caused by multiple distributed logic devices on the same trace.... don't we?
And added distributed capacitance also reduces the Zo of a trace which causes
local reflections and reduces noise margins. After all, these complications
to the "ideal" equations are WHY there is a technical specialty called signal
That said, these quirky interrelationships afford fun and interesting
challenges to us all...and may sometimes be rewarded with the respected
"guru" tag from younger engineers who are just getting their feet wet. Life
is great, isn't it?
Have a great St. Patrick's Day and a good weekend of R&R,
Michael L. Conn
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