Re: [SI-LIST] : PLL clock buffer chips and the feedback loop

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From: Arrigo Benedetti ([email protected])
Date: Mon Apr 03 2000 - 11:47:07 PDT

"Andy Peters" <[email protected]> writes:

> When using "zero-skew" PLL clock buffer chips (such as the Cypress
> RoboClock), where do you bring the feedback from? Cypress' data sheets and
> app notes are notoriously (and typically, I might add) unclear on this -
> they simply indicate that it comes from "one of the outputs."
> For instance, my board has an FPGA that talks to four SDRAM devices. It
> seems to me that one buffer output could drive the FPGA's clock pin (via
> series termination) and four of the other outputs could drive the four SDRAM
> clocks (again, through series terminations). Assume that my clock line
> lengths are equal, to minimize board skew. Do I take the feedback from one
> of the destination pins, and match the line length? Or is it sufficient to
> simply connect one of the outputs to the feedback pin right at the chip?

Hi Andy,

what you should do is to run a trace from one of the RoboClock
outputs that is not driving any other device and route it back to the
RoboClock feedback input. This trace, as well as the traces feeding the
clocks to the FPGA and the SDRAM's, should all be matched in lenght.
Another option, if you use Xilinx Virtex devices, is to use their internal
DLL if your input clock frequncy is not below 25 MHz.

> Are there any other vendors of these sorts of devices? Spread-spectrum
> capability is not required.

You can check Microclock, Motorola and Synergy semiconductors (now IDT I



Dr. Arrigo Benedetti                e-mail: [email protected]
Caltech, MS 136-93	  			phone: (626) 395-3695
Pasadena, CA 91125	  			fax:   (626) 795-8649

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