RE: [SI-LIST] : montonic signals at SDRAM-, SSRAM- and FEPROM-ad ress inputs

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From: L· (John@quantatw.com)
Date: Fri Feb 11 2000 - 00:21:51 PST


Dear Dirk,

Naturally, synchronized circuit is good in immunity of noise, including the
non-monotonic on transient edges, rising or falling, as long as the setup
time and hold time of signal are met.

However, Non-monotonic edges, caused by reflection of
signal, may generate high frequency noise and create EMI, crosstalk, ground
bounce, and ISI problems. Those will degrade system noise margins.

 

John Lin
SI Engineer
Quanta Computer Inc.,Taiwan, R.O.C.
Email: John@quantatw.com
Tel: 886+3+3979000 ext. 5183

-----Original Message-----
From: Netzler Dirk [mailto:Dirk.Netzler@icn.siemens.de]
Sent: Friday, February 11, 2000 3:02 PM
To: 'si-list@silab.eng.sun.com'
Subject: [SI-LIST] : montonic signals at SDRAM-, SSRAM- and
FEPROM-adress inputs

Hello All,

every time I have to design memory buses I wonder wether signals at adress
inputs
of synchronous memory chips (SDRAM, SSRAM) ) must have monotonic edges or
not.
If yes, can anybody give me an explanation for that ?

And what's about FEPROMs ? Okay, the control signals (e.g. WE,OE) need to be
monotonic.
But what's about the adress inputs ? Should they be monotonic, too ? I don't
find reasons for that.

What are your experiences ?

Best regards

Dirk Netzler
Siemens AG

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