[SI-LIST] : Crossing clock domain boundaries in digital ASICs

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From: volker.nicolai@philips.com
Date: Fri Feb 04 2000 - 02:13:01 PST


Hi,

I asked this question at sci.electronics.design and comp.arch.fpga newsgroups
already and did not yet get a satisfying answer, hope I do here :-):

I'm looking for the best solution of crossing clock domain boundaries in
digital designs solving the related timing problems.
In scan pathes lock-up latches are common (like Synopsys inserts them
during scan insertion).
Why negative (level triggered) latches instead of negative (edge
triggered) FFs? Is the setup/hold problem at the FALLING clock edge the
reason. which I do not have with latches (according to my simulations) ?
Couldn't I use them in functional pathes too?
Should I more concentrate on the adjustment of the clocks of the
different modules in my design or more on the datapathes. It seems easy
if the datapath is unidirectional but if it goes in both directions?

More detailed: At the moment I have clocks which have a common frequency
base (like 32 Mhz and 64 Mhz). The phase relation is
at least not yet predictable as the clocks are driven by seperate
clocktrees (for each frequency) which we not yet have
inserted. I look for a solution to avoid problems with clock adjustment
after layout (clock tree insertion) and the timing on
pathes that originate in one domain and end at the other.

Any comments, help or hints for information sources are very welcome.
Volker

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