Re: [SI-LIST] : Board simulations, what should it include?

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From: James Antonellis - Sun BOS Hardware (janton@neworleans.east.sun.com)
Date: Tue Mar 14 2000 - 10:24:18 PST


yehuda,

I'm sure you'll get a lot of good answers to this one...

I'll give it some of my (novice) thoughts:

0- Assumption from your reference to email that HSPICE
   will be your predetermined sim environment.
   
1- The answer to this is depends. That is, depends on what
   you are looking for. E.g. simple reflective termination
   scheme trials, or coupled x-talk/package SSN etc. etc??
   In particular, if you are just looking at reflections
   for example, then the input structure of an SDRAM may
   be inportant if it contains clamping diodes... again
   just an example. The point is, you may have enough for
   some simple tasks but not enough for another simple task;
   depends on what your looking for.
   
   A case in point is an n-th level spice deck I assembled
   to look at a problem some time ago. I had lumped vias, mutual
   pkg terms etc. etc. all it did for me was take up CPU cycles
   as a simple 1st level model showed the same phenom I was hunting!
   Good lesson learned in that case.
   
2- I like to make use of a pkg model when it is available. This
   suggests the required model validation (not discussed here)
   step although.
   
3- Speaking of preferences, I like the W-Element, but have used
   the U and T for very simple tasks. The HSPICE doc set discusses
   the application limitations nicely. Also, lots of archive on
   this reflector for W-Element. (Note the W-Element was driven
   by the RLGC matrix).
   
4- Some Einstein comment about keeping it as simple as possible
   but not too simple pops up in my mind.
   
If you need to, you can contact me off-line and I can give some
more details,

jim

   
> From: "Yehuda D. Yizraeli" <yehuda@zoran.co.il>
> To: "silist" <si-list@silab.eng.sun.com>
> Subject: [SI-LIST] : Board simulations, what should it include?
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> Hi,
>
>
> I am trying to simulate a chip driving an SRAM and a flash
memory. My chip
> is modeled with its output buffer, a trace to the SDRAM (modeled as
> transmition line), then the SDRAM is modeled with lumped capacitor,
series
> matching resistor, another transmition line and the flash chip.
>
> 1) Do I model it correctly?
> 2) Should I add to the loading chips the inductance of the package OR
timing
> simulation should use package load as capacitor only (for the driver
chip I
> had added package inductor and resistor).
> 3) Whats the appropriate transmition line model ishould use in HSPICE
> 4) Any other comments/suggestions?
>
>
>
> thanks in advance, yehuda
>
>
>
> -------------------------------------------------------------------
> Yehuda D. Yizraeli
>
> Zoran Microelectronics Ltd. E-mail : yehuda@zoran.co.il
> Advanced Technology Center Direct Tel: 972-4-85-45-795
> P.O.B. 2495, Haifa 31204, Operator : 972-4-85-45-777
> ISRAEL Cellular : 972-52-556-335
> http://www.zoran.com Fax : 972-4-8-551-550
> -------------------------------------------------------------------
>
>
>
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-
Jim Antonellis Sun Microsystems
jim.antonellis@sun.com Workgroup Servers
(781) 442-0392 Burlington, MA. 01803

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