From: Eric Anderson ([email protected])
Date: Mon Apr 17 2000 - 15:12:42 PDT
--- Robison Michael R CNIN <[email protected]> wrote:
> hello,
>
> i hope that i'm posting correctly here. i'm laying
> out a board and
> thinking i'll have 9 layers:
>
> sig
> +5V
> sig
> sig
> gnd
> sig
> sig
> -15V
> sig
>
Hi Michael -
It depends on what you're trying to achieve. If you have
high-frequency signals running adjacent to the +5V or -15V
planes, those signals will in effect be referenced from an EM
point of view back to those planes. But inside any given chip
most likely the reference (for driving and for receiving) of
those signals will still be referenced to ground. So effects
from return currents could become significant. Decoupling caps
can help make the voltage planes "look" more like a ground plane,
but the plane + via + cap combination is a poor substitute for
the real thing (a ground plane to reference to) at higher edge
rates.
But at 25-MHz using 5V CMOS logic levels, as long as your trace
lengths aren't too long, this stackup might actually work
okay for you, especially with the slower edge rates of the ALS
devices that you mentioned.
However, if you are concerned about reducing overall EMI
from the board, especially if you are looking at higher edge
rate parts, you might want to reconsider not having the
extra ground planes to go with the outer signal layers.
Good luck.
-Eric Anderson
[email protected]
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