Re: [SI-LIST] : different 4-layer board Stack up (S-P-G-S) ?

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From: ajmani@us.ibm.com
Date: Tue Mar 07 2000 - 10:14:33 PST


Brent,
I agree with you that with a board thickness of 0.062", you will have very
long vias if you want to keep power and ground planes close together. I
think it is about time that we got rid of this so called standard board
thickness of 0.062", particularly for 4-layer boards. For high speed board
design, it is so much more advantageous to have good buried capacitance,
that I would rather go for a non-standard board thickness.

By the way, can someone enlighten me on how 0.062" came to be the standard
board thickness.

Regards,

Ravinder Ajmani
PCB Development and Design Department
IBM Corporation - Storage Systems Division
Email: ajmani@us.ibm.com
***************************************************************************
Always do right. This will gratify some people and astonish the rest.
.... Mark Twain

brent.dewitt@us.datex-ohmeda.com@silab.eng.sun.com on 03/07/2000 09:40:48
AM

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Subject: Re: [SI-LIST] : different 4-layer board Stack up (S-P-G-S) ?

Ravinder,

If your ending up with an 0.062" board, does that leave you with some
pretty
high inductance ground vias? With a four layer board at moderate speed
(3-4
nsec edge rates), I'm constantly questioning which will give me the best
results, lowering the trace impedance by making the ground plane to signal
layer
spacing small, or making the ground to power plane spacing small for
decoupling.
Unfortunately, no one here wants to make 0.015" thick boards ;}

Best regards,

Brent DeWitt

ajmani@us.ibm.com on 03/07/2000 10:17:42 AM

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Subject: Re: [SI-LIST] : different 4-layer board Stack up (S-P-G-S) ?

I do not think that a power plane is any more noisier than the ground
plane. A well decoupled power plane will behave similar to a ground plane.
In addition, I would keep the spacing between power and ground planes close
to 3-4 mils, to ensure good high-frequency decoupling. With the top layer
real estate used up by the components, and power plane sectioned to
accommodate different voltages, it becomes necessary to have S-P-G-S
stackup, where one can get ample routing space on the bottom layer, all
referenced to a contiguous ground plane. One can use two extra ground
layers in special circumstances to reduce the EMI, but it is not economical
for normal designs.

Regards,
Ravinder Ajmani
PCB Development and Design Department
IBM Corporation - Storage Systems Division
Email: ajmani@us.ibm.com
***************************************************************************
Always do right. This will gratify some people and astonish the rest.
.... Mark Twain

"Shawn X. Arnold" <sarnold@cpcibackplanes.com>@silab.eng.sun.com on
03/07/2000 08:39:09 AM

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To: <si-list@silab.eng.sun.com>
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Subject: Re: [SI-LIST] : different 4-layer board Stack up (S-P-G-S) ?

Take a look at reversing the power and gnd planes in the stackup. The
noisiest thing on the PCB is the power plane, even with good decoupling.
Using a standard 4 layer construction, i.e. a .038 core in the middle, the
power plane, layer 2 in your stackup, is 3X closer to the SMD pads than it
is to the gnd plane. A lot of the digital switching noise will couple to
the SMD pads and could lead to radiated emissions problems. Also, change
the core thickness to get a more desirable impedance. Don't just let the
fab house run it with their "standard" core thickness. Once you have the
impedance that you want across most of your PCB, you can modify the trace
width on things like the SCSI bus to push the impedance back?to 100 ohms.

Shawn Arnold
International Product Design Inc.
-----Original Message-----
From: Alex Li <alexl@ati.com>
To: 'si-list@silab.eng.sun.com' <si-list@silab.eng.sun.com>
Date: Monday, March 06, 2000 6:53 PM
Subject: [SI-LIST] : different 4-layer board Stack up (S-P-G-S) ?

Recently?I saw a 4-layer mother board with 100 Mhz?128-bit memory bus.
This board has unusual signal-power-ground-signal?stack up.?I talked to
one of their engineer for this kind of arrangement.?They said since most
PC motherboard has several power plane split and on the top level there
are a lot of components with pads. they think if they route all the
128-bit memory bus on the back and put it close to ground plane, they have
much routing area and this will help to keep the signals clean.

???This is kind of new idea to me,?does anyone see any drawback by this
arrangement ??Will this decrease the decoupling caps performance ?

??????????????????????????????????????????????? Alex

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