From: Ingraham, Andrew ([email protected])
Date: Mon Feb 14 2000 - 11:05:07 PST
>If you look at the specs for SDRAM you will find that the timing
>is only specified for specific edge rates.
That is true of just about every digital IC, not just SDRAMs.
(Maybe SDRAMs are more sensitive to edge rate variation than other parts, I
> (Remember this is "synchronous memory.) They drive almost
>directly into the device column and row amplifiers of the array which is
>a good place meta stable events to occur.
Um, I thought synchronous memory (as in SDRAMs) means the input is clocked
into a latch or flop, before being passed on to the column and row
One would hope (in fact, by definition it is supposed to be) that a clocked
device, such as these input flops into which the address, data, and controls
are latched, require stable inputs ONLY within a window of time, between the
Setup time before clock, and the Hold time after clock; and are insensitive
to changes on those inputs at all other times.
If these flops are imperfect such that they are sensitive to their inputs at
other times, then either the Setup/Hold time specs are wrong, or they forgot
to include a disclaimer saying why their parts don't behave according to
established practice for clocked devices.
Generally speaking, the clock to an SDRAM/SSRAM must be monotonic, but
everything else shouldn't matter. If that is not how they behave, then
someone's holding back on us.
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