Re: [SI-LIST] : Fast edges with limited plane capacitance

About this list Date view Thread view Subject view Author view

From: Fred Balistreri (fred@apsimtech.com)
Date: Fri Mar 17 2000 - 11:37:21 PST


Absolutely, there are trade offs. However if one can deal with the
impedance and cross talk aspect of the s-s-G-P-s-s through
good routing and SI techniques (simulation included) then this
stackup becomes preferable. The reason is simple. Radiating
antenna problems from surface microstrips are easily contained
with a good shield (box). However high frequency noise introduced
into the power delivery system is not so easily fixed, can result in
high common mode EMI and very expensive solutions...re-spin of
the board being one. The reason is simple once the power/gnd
become noisey the box (shield) itself cannot be relied upon and
can radiate as well. Any cable or subsystem attached to the
board may cause problems as well. In any case the tradeoffs of
the two need to be carefully thought out and engineered. And of
course the mileage you get very varies greatly with the application
involved.

Best Regards,

Doug McKean wrote:

> mjs wrote:
> >
> > Let's assume that a power subsystem has a low, flat impedance up to a few
> > hundred MHz, and has a pair of realtivly unbroken planes. Only problem is
> > that the stackup is s-G-s-s-P-s since the engineer has insisted that EMI
> > will be a problem unless all noisy digital signals are 'sandwiched'
> > between the planes. This board also has parts with 1-2ns edge rates.
> >
> > I am arguing that s-s-G-P-s-s is the preferred stackup, as this would
> > allow the planes to be 4-5mils apart instead of 40mils on an .062" card,
> > yielding much greater plane capacitance.
> >
> > My questions is this: How does a lack of planar capacitance contribute
> > to increasing EMI? It seems that not having the proper plane capacitance
> > would tend to slow edge rates and possibly be one of the lesser SI sins.
> >
> > Also: Is there any validity to the s-G-s-s-P-s 'copper sandwich'
> > decreasing EMI?
>
> I would start the discussion by saying the
> question stems from mixing actually two
> entirely different concepts:
>
> 1. Near field effect decoupling,
> i.e. interplanar capacitive effects
>
> versus
>
> 2. Far field effect shielding,
> i.e. shielding effectiveness
>
> While the s-s-G-P-s-s stackup allows for better
> decoupling between G-P, it can also lead to poor
> far field performance, which is difficult to predict
> to say the least, and is dependent upon not only
> planar but interplanar routing of traces, etc ...
> But then, there is no shielding effectiveness of
> the traces to the outside world.
>
> The s-G-s-s-P-s stackup allows one to "bury" high
> speed/fast edge rate and clock signals into the
> middle two planes with the shielding effectiveness
> of the G and P planes. *Possibly* at the cost of
> decoupling the G and P planes. - Doug McKean
>
> **** To unsubscribe from si-list or si-list-digest: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
> si-list archives are accessible at http://www.qsl.net/wb6tpu
> ****

--
Fred Balistreri
fred@apsimtech.com

http://www.apsimtech.com

**** To unsubscribe from si-list or si-list-digest: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu ****


About this list Date view Thread view Subject view Author view

This archive was generated by hypermail 2b29 : Thu Apr 20 2000 - 11:35:43 PDT