Re: Fw: [SI-LIST] : via capacitance

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From: cadpro2k@dacafe.com
Date: Mon Apr 10 2000 - 11:50:55 PDT


Hi all,

Is it me, or is it just me, but I would NEVER sandwich 4 signal layers
together, regardless of the planes capacitance techniques. There are way
too many issues to cause havoc with the pcb.

Just my $.002 worth.

BTW, I much prefer Sunil's stackup over Jon's suggestion.

Mitch

---------Included Message----------

> Jon Keeble wrote:
>
> > Following advise from this list, for 10 layer boards I prefer
the following
> > stackup:
> >
> > LAYER1 TOP LAYER (CONDUCTOR)
> > LAYER2 VCC
> > LAYER3 GND
> > LAYER4 CONDUCTOR
> > LAYER5 CONDUCTOR
> > LAYER6 CONDUCTOR
> > LAYER7 CONDUCTOR
> > LAYER8 VCC
> > LAYER9 GND
> > LAYER10 BOTTOM LAYER (CONDUCTOR)
> >
> > This puts the power planes close together (maxim distributed
capacitance)

> > >-----Original Message-----
> > >From: Sunil Kumar <sunilb@cdotb.ernet.in>
> > >>I am using a multilayer board having the following stack-up:
> > >>
> > >>LAYER1 TOP LAYER (CONDUCTOR)
> > >>LAYER2 GND
> > >>LAYER3 CONDUCTOR
> > >>LAYER4 CONDUCTOR
> > >>LAYER5 VCC
> > >>LAYER6 GND
> > >>LAYER7 CONDUCTOR
> > >>LAYER8 CONDUCTOR
> > >>LAYER9 GND
> > >>LAYER10 BOTTOM LAYER (CONDUCTOR)
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