Re: [SI-LIST] : trace width for clock routing- wider/narrower?

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From: Vinu Arumugham (vinu@cisco.com)
Date: Mon Mar 13 2000 - 09:47:26 PST


Even if the Rout of a clock driver is low, it may not be designed to drive a low impedance line.

Trace spacing requirement is more a function of the height over the reference plane than trace width. So, 10 mil lines, like 5 mil lines can also be used with a 10 mil spacing when using say a 5 mil
dielectric.

A low impedance clock line can be used to provide a better edge rate and improve jitter at the receiver.
Another possibility is to use a 33 ohm line to supply two loads using electrically long, matched 66 ohm stubs.

Multiple outputs of some clock drivers can be shorted together to drive low impedance lines.

Vinu

"S. Weir" wrote:

> Weber,
>
> I look at this as matching the driver. If the driver has substantial
> impedance then a series term will be the easiest. For most clock drivers,
> that will require a discrete resistor with all the attendant
> "benefits". If your driver can couple directly into the trace( because it
> is designed to ), I think you are better off without the resistor.
> Modelling should give you a good answer about what is adequate for a
> particular situation.
>
> 1. I do not believe that within the practical limits we are talking about a
> wider trace produces more or less EMI, provided it is matched to the real
> impedance of the driver / receiver network, and as you have stipulated, the
> return path is good. A wider trace should yield more accurate impedance.
>
> 2. Then I think the return path needs to be fixed. If the return path is
> seriously compromised, the EMC and SI problems are going to be very tricky
> to solve. You can look back about two weeks where Lee Ritchey quoted that
> one of the most common problems he has to solve results from poor returns
> do to misapplied moating. ( Lee please jump in if I am misquoting you. )
>
> Good planning, enough decoupling, enough power / gnd vias, and good
> modelling / verification should get through the day for PC's. ( Unless of
> course you are fighting RAMBUS on 4 layers, in which case intervention by a
> deity may be called for ).
>
> Regards,
>
> Steve.
> At 10:34 AM 3/13/2000 +0800, you wrote:
> >Hi all,
> >
> > I think John's question resides in that should 5 mils or 6 mils or maybe
> >8mils or 12 mils of trace width should be used, since we all know that
> >coupling is in inverse proportion(to some order) to the trace spacing,
> >especially in the PC platform design today, the clock generator usually
> >shows a Rout of about 30~40 Ohm, and to match the impedance , a trace width
> >of 8~15 mils should be used, or a series resistor(maybe 10~33 Ohm) has to be
> >used, why such a contradiction exists? For better real estate efficiency, 5
> >mils trace is the most popular one, yet the Rout is so low that we might
> >need to use series termination? Here I want to summarize my question also
> >and may have your kind and valuable comment and help.
> >1. will a wider trace cause more EMI issue than a narrower trace with a
> >series term if the Rout is small? (Assume that the return path is good).
> >2. If the return path is somewhat ruined because there are so many power
> >level in the PC design today, then which one would be impacted more than the
> >other one? I mean in SI regard and EMI regard.
> >
> >
> > Best Regards
> > Weber Chuang( e)
> > Signal & Timing Integrity Engineer,
> > VIA Technologies, Inc. Taipei, Taiwan, ROC
> > TEL : 886-2-22185452 ext : 6522
> > mailto:weber@via.com.tw <mailto:weber@via.com.tw>
> > http://www.via.com.tw <http://www.via.com.tw/>
> > Very Innovative Architecture
> >
> >
> >
> >-----Original Message-----
> >From: S. Weir [mailto:weirsp@a.crl.com]
> >Sent: Monday, March 13, 2000 9:29 AM
> >To: si-list@silab.eng.sun.com
> >Subject: Re: [SI-LIST] : trace width for clock routing- wider/narrower?
> >
> >
> >John,
> >
> >Assuming stripline or microstrip construction, set the trace width to get
> >the required impedance and set the spacing to get the required crosstalk
> >isolation. The amount of attenuation for a given amount of spacing required
> >depends largely on the height to the nearest reflection plane, and the
> >parallelism to other traces. If 5/10 gives you 50 ohms, then 5/25 will give
> >roughly 6X the attenuation for any amount of parallelism beyond the critical
> >length that 5/10 gives you and still maintain 50 ohms.
> >
> >The above does not hold true if you are using coplanar waveguide. There
> >were various discussions of CPW characteristics on this thread about a month
> >ago.
> >
> >Regards,
> >
> >
> >Steve.
> >At 09:04 AM 3/13/2000 +0800, you wrote:
> >
> >
> >
> >Dear All SI experts,
> >
> >For clock routing, does wider trace width have more advantage than narrower
> >one ,in term of better electrical properties, under the condition of same
> >trace to space ratio and good match in impedance with source terminators?
> >
> >For example, 5 mils trace width with 10 mils trace spacing versus 10mils
> >trace width with 20 mils trace spacing.
> >
> >Thank you for your helps in advance.
> >
> >John Lin
> >SI Engineer
> >Quanta Computer Inc.,Taiwan, R.O.C.
> >Email: John@quantatw.com
> >Tel: 886+3+3979000 ext. 5183
> >
> >
> >
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