Re: [SI-LIST] : low ESR decoupling capacitors

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From: Adrian Shiner (adrian.shiner@virgin.net)
Date: Fri Jan 07 2000 - 12:52:53 PST


Aubrey,
I'm not taking them out of context, far from it. Larry demonstrates that
thinking laterally produces new & good solutions to problems. He also
demonstrated that large currents can flow but suffering no ill effects from
them. I often throw a maybe wild thought into these discussions just to help
"break the mould" on rigid thinking, or thinking based on maintaining the
status quo in business terms. I have found that doing this throughout my
career has prompted many new approaches to the way things are done (not just
electronics). Some fashionable thinking on managing R&D calls it "kissing
the frogs". Many times, it is a bad experience, occasionally you get a
princess in your hands.

Happy days

Adrian

----- Original Message -----
From: <Aubrey_Sparkman@Dell.com>
To: <si-list@silab.eng.sun.com>
Sent: 06 January 2000 19:32
Subject: RE: [SI-LIST] : low ESR decoupling capacitors

> Adrian,
> Be careful you don't take Larry's excellent comments out of context.
Large
> currents in the right place make the best antennas (experience in low
> frequency radio transmitters).
>
> While voltage based logic may not be the best, you haven't said how you
get
> from one subject (radiation) to the next (signaling techniques). You may
> find that impedance control (or lack thereof: discontinuities) determines
> radiation, not the size of voltage or current.
>
> Aubrey Sparkman
> Signal Integrity
> Aubrey_Sparkman@Dell.com
> (512) 723-3592
>
>
> -----Original Message-----
> From: Adrian Shiner [mailto:adrian.shiner@virgin.net]
> Sent: Thursday, January 06, 2000 1:10 PM
> To: si-list@silab.eng.sun.com
> Subject: Re: [SI-LIST] : low ESR decoupling capacitors
>
>
> The comments about large currents not causing EMI problems lend some
support
> to my thoughts that voltage based logic is not the necessarily the best
way
> of designing computers.
>
> Adrian
> ----- Original Message -----
> From: Larry Smith <Larry.Smith@Eng.Sun.COM>
> To: <si-list@silab.eng.sun.com>
> Sent: 05 January 2000 21:46
> Subject: Re: [SI-LIST] : low ESR decoupling capacitors
>
>
> > DC - the calculations below are just an example for one capacitor.
> >
> > To build a robust power system, we need many different valued
> > capacitors in parallel. The list probably includes some 100nF, 10nF,
> > 4.7nF, 3.3nF, 2.2nF, 1.5nF, 1nF, 820pF, 680pF, 470pF, as well as bulk
> > capacitors. Each capacitor value resonantes and presents a minimum
> > impedance to the power distribution system at a different frequency.
> >
> > To calculate the number of each value to put in parallel, we have to
> > know the ESR. Then it is just a simple matter of putting enoungh
> > capacitors of each value in parallel to reach down to a target
> > impedance. We might end up with 100 capcitors in parallel, some of
> > each value. The impdeance over frequency becomes flat and resisitive
> > in phase. It is quite practical to have a flat 10 mOhm impedance out
> > to 100 MHz or more with 100 capacitors. The phase of the parallel
> > impedances does not deviate very far from being resistive.
> >
> > You can hit that power system with any clock pulse or any conceivable
> > current load waveform and see noise similar to what you would see with
> > an ideal voltage source with a 10 mOhm series resistor. It is very
> > difficult to predict the load waveform that customer code is going to
> > cause the uP and ASICs to draw from the power system. Therefore, we
> > want to have a flat impedance across a broad frequency range.
> >
> > This makes an almost ideal supply. If your system needs a 5 mOhm
> > supply, just double the number of capacitors (...or halve the ESR of
> > the capcitors you already have...). There is no voltage ringing in the
> > overall system because of the flat impedance profile.
> >
> > There is however tremendous current ringing back and forth between
> > capacitors. We have not seen an EMI problem from this. In fact, the
> > EMI performance of the systems that we have built from this methodolgy
> > have always shown an EMI improvement. It seems that power planes with
> > bouncing voltages are more harmful than power planes that redistribute
> > a lot of current.
> >
> > regards,
> > Larry Smith
> > Sun Microsystems
> >
> > > From: "D. C. Sessions" <dc.sessions@vlsi.com>
> > >
> > > Larry Smith wrote:
> > > >
> > > > Doug - I am changing the thread title to better reflect the subject.
> > > > We need to take a look at inductance, resistance and capacitance
> > > > to determine the impedance of a capacitor at 200 MHz. If you follow
> > > > this through, you will see the great value of low ESR capacitors.
> > > >
> > > > Inductance is probably the most important parameter of a decoupling
> > > > capacitor. You have correctly calculated the inductive reactance of
a
> > > > typical capacitor at 200 MHz if it is mounted on 5 nH pads. But
with
> > > > careful pad and via design, we routinely reduce the mounted loop
> > > > inductance of 0805 size capacitors to less than 1 nH. One nH gives
us
> > > > 1.26 Ohms of inductive reactance at 200 MHz.
> > > >
> > > > But, suppose we mount a 633pF capacitor with 100mOhms ESR on that 1
nH
> > > > pad. It forms a nice series RLC circuit that has a minimum
impedance
> > > > at frequency 1/(2pi*sqrt(LC)) = 200 MHz. The impedance is:
> > > >
> > > > R + jwL + 1/jwC
> > > > = 100m + j 1.26 - j 1.26
> > > > = 100mOhm
> > >
> > > The problem is that most of us aren't trying to draw narrow-bandwidth
> > > sinusoidal power from the supply network. For us, the wild resonant
> > > swings on the capacitors aren't neatly balanced by equally wild di/dt
> > > swings on the inductance, and instead the local supply gets sucked
> > > down hard at clock edges and then swings out of safe operating area
> > > in between.
> > >
> > > I'm somewhat familiar with the work being done on resonant clock/power
> > > systems, but since our libaries and processes aren't designed with
> > > them in mind I really would prefer a supply net that minimized peak
> > > excursions from nominal over one that was nominal only at selected
> times.
> > >
> > > > By using a low ESR capacitor, we have presented an impedance to the
> > > > power distribution system that is 1/10 of the impedance from the
> > > > inductance.
> > > >
> > > > This is an extremely powerful concept. With low inductance mounting
> > > > pads and low ESR capacitors, it is possible to build a high
> performance
> > > > power distribution system with a fraction of the capacitors you
might
> > > > have thought you needed. You just have to carefully pick the
> > > > capacitance value, carefully design the pads, and have a source of
low
> > > > ESR caps. THE LOWER, the BETTER!
> > > >
> > > > We are designing power distribution systems with target impedances
> that
> > > > are less than 10 mOhms. Typical NPO and X7R capacitors in the 470
pF
> > > > to 10 nF range have ESR greater than 100mOhms. We could use
> capacitors
> > > > that have 1/10 the ESR of today's caps. We could reduce the number
of
> > > > capacitors cluttering up or boards from hundreds to tens. If we
only
> > > > had lower ESR caps...
> > > >
> > > > We do not sprinkle in capacitors like salt and pepper but rather
have
> a
> > > > very deliberate design methodology. It is documented in the IEEE
> Journal
> > > > Transactions on Advance Packaging, Aug 1999, Vol 22, Number 3. The
> > > > paper gives much more details on power distribution and decoupling
> > > > capacitors than I can give in this space. A soft copy is available
> at:
> > > >
> > > > http://www.qsl.net/wb6tpu/si_documents/docs.html
> > > >
> > > > Parallel capacitor resonance is definitely an issue. You must have
a
> > > > methodology that avoids the parallel resonance if you are going to
use
> > > > low ESR capacitors. You must carefully design the power plane
> stackup.
> > > > Placement is critical for capacitors that resonate at a frequency
> where
> > > > the dimensions of the board become significant. But fortunately,
> > > > software tools will soon become available in the public domain to
help
> > > > us do all of this.
> > > >
> > > > Now, all we need is low ESR caps.
> > > >
> > > > BTW, I really like your time domain method of measuring capacitor
> > > > parameters. You won't get any information about mounted inductance
> > > > from this measurement, but capacitance, ESR and fixture inductance
> > > > determine the shape of the observed waveform. Is there some reason
> > > > why you use a 100 Ohm resistor to inject energy into the cap? A 50
> > > > Ohm resistor might better terminate the transmission line and avoid
> > > > transmission line resonance issues in the measurement.
> > > >
> > > > regards,
> > > > Larry Smith
> > > > Sun Microsystems
> >
> >
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