[SI-LIST] : Low EMI on Two layers

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From: Fred Dieckmann (Fred.Dieckmann@usa.alcatel.com)
Date: Fri Feb 04 2000 - 07:21:45 PST


I recommend three very good books on the subject.

Introduction to Electromagnetic Compatibility by Clayton Paul

High Speed Digital Design by Howard Johnson

EMC and the Printed Circuit Board: Design, Theory, and Layout
Made Simple by Mark I. Montrose

I did an EMI reduction layout, staying on two layers and achieved 8 dB
or more reduction at several frequencies and 12 dB at a couple of
frequencies.

Minimize loop area of you noisiest traces by putting return
traces for the ground currents very close to signal traces.
 
Optimize placement to keep noisiest traces short as possible.

Put small planes under noisy ICs where possible.

Use ground and Vcc gridding and put good decoupling caps as close to
power and ground pins as possible with short wide leads.

The signals with the fastest edge rates and the most repetition
(clocks, strobes, and serial data) will be you worst radiators.

Use good signal integrity wherever possible and correctly terminate
fast signal and clocks. Good signal integrity usually makes for low
EMI.

I had several people tell me that we had to go to 4 layers to get low
EMI but we would have had to spend another 2 dollars on a board we plan
to build a million of a year! Give it a try, we were very suprised at
how quiet we got on only two layers on a board with a Micro, RAM, and an
ASIC and several analog and digital ICs. Of course now I have to do
the same for several other cards.....

Good Luck,

Fred Dieckmann

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