RE: [SI-LIST] : Power Plane for Internal Device Power?

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From: Peterson, James F (FL51) (james.f.peterson@honeywell.com)
Date: Fri Jan 28 2000 - 04:19:58 PST


If this is true, then we don't have to use up a layer for a core's internal
voltage supply?

Tony wrote "If I have a device whose I/O are 3.3V and internal logic is
powered from 1.8V do I need a power plane to supply that 1.8V or will a
power strip to that device suffice?"

I will have to deal with this issue in the coming months - I am very
interested in more feedback from chip and board people out there in the
"know".

thanks a lot.
Jim

-----Original Message-----
From: D. C. Sessions [mailto:dc.sessions@vlsi.com]
Sent: Thursday, January 27, 2000 5:29 PM
To: si-list@silab.eng.sun.com
Subject: Re: [SI-LIST] : Power Plane for Internal Device Power?

Lee Ritchey wrote:
>
> What you will need is a plane large enough to provide plane capacitance
large enough to support the very fast switching transients that the 1.8V
supply
> will be required to support.

Not really. Package inductance is enough to make a chip nonfunctional
if it has to go off-chip for logic transients (e.g., clock edges). They
have to be supplied from onchip capacitance, and the bondwires even
limit how much of that noise leaks out. External capacitance is only
useful for stuff in longer time domains, such as power management of
blocks' gated clocks.

> phelan, tony wrote:
>
> > If I have a device whose I/O are 3.3V and internal logic is powered from
> > 1.8V do I need a power plane to supply that 1.8V or will a power strip
to
> > that device suffice? Another way of asking this I guess would be: Are
all
> > return path currents for the internal 1.8V signals handled internally to
the
> > device. If so then there would be no advantage to making the 1.8V supply
a
> > plane?
> > Any comments on this would be appreciated.
> >
> > Tony Phelan
> > EMC Corporation
> >
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-- 
D. C. Sessions
dc.sessions@vlsi.com

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