[SI-LIST] : Stack up

About this list Date view Thread view Subject view Author view

From: Iulian Ungureanu (Iulian_Ungureanu@pmc-sierra.com)
Date: Mon Feb 21 2000 - 11:23:09 PST


Hi

I'm listening to this list for some time now and I would like to ask your
opinion on a stack-up I'm working on.
        It is a board with 4x64 pairs of LVDS signals, 77.76 MHz clock, high
speed(777.6 Hb/s).

        I came up with a 14 layers that looks like that:

Signal top fanout, some analog power
1.8V
Gnd
Sig1 LVDS
Sig2 LVDS
Gnd
Sig3 LVDS
Sig4 LVDS
Gnd
Sig5 LVDS
Sig6 PECL clocks
3.3V
Gnd
Signal bottom fanout

        I'll be using 1.6 mil core for my high speed cap.
        I would gladly use less layers, but I'm being forced by the HS3
connectors.
        
        I would really appreciate your opinion.

Thanks,

Iulian Ungureanu
PCB Designer
PMC-Sierra,Inc.
Iulian_Ungureanu@pmc-sierra.com
http://www.pmc-sierra.com
Voice:(604)415-6053 Ext.2586
Fax:(604)415-6206

**** To unsubscribe from si-list or si-list-digest: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
****


About this list Date view Thread view Subject view Author view

This archive was generated by hypermail 2b29 : Thu Apr 20 2000 - 11:35:07 PDT