From: Iulian Ungureanu (Iulian_Ungureanu@pmc-sierra.com)
Date: Mon Feb 21 2000 - 11:23:09 PST
I'm listening to this list for some time now and I would like to ask your
opinion on a stack-up I'm working on.
It is a board with 4x64 pairs of LVDS signals, 77.76 MHz clock, high
I came up with a 14 layers that looks like that:
Signal top fanout, some analog power
Sig6 PECL clocks
Signal bottom fanout
I'll be using 1.6 mil core for my high speed cap.
I would gladly use less layers, but I'm being forced by the HS3
I would really appreciate your opinion.
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