RE: [SI-LIST] : monotonic signals at SDRAM-, SSRAM- and FEPROM-a dress inputs

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From: Peterson, James F (FL51) (james.f.peterson@honeywell.com)
Date: Wed Feb 16 2000 - 12:44:39 PST


Scott,
Thanks for the insight, but I am a little confused (it might be that I'm not
familiar enough with Sync memory).

You Stated :
"So, a glitch in the
edge can cause several pulses, or even runt pulses to be passed from the
input receiver to subsequent latches in the devices. These device latches
do not have any additional stages to reduce the probability of metastability
events. (Remember this is "synchronous memory.) They drive almost
directly into the device column and row amplifiers of the array which is not
a good place meta stable events to occur."

If this is synchronous memory, then the non-monotonic address line doesn't
get past the register that is clocking it. No problem. I'm assuming that
they are registered and this may be where I'm confused.

Now if they are registered, and the transition occurs within the setup-hold
window, then it's a no-no if it's monotonic or non-monotonic......But the
original question was, if we have non-monotonic edges, outside the clock
region, why is that harmful?

asynchronously confused,
Jim

 

-----Original Message-----
From: Scott McMorrow [mailto:scott@vasthorizons.com]
Sent: Monday, February 14, 2000 11:49 AM
To: si-list@silab.eng.sun.com
Subject: Re: [SI-LIST] : monotonic signals at SDRAM-, SSRAM- and
FEPROM-adress inputs

James,

If you look at the specs for SDRAM you will find that the timing
is only specified for specific edge rates. Usually 1V/ns. Sometime
down to as low as .5 V/ns. These are specified within the
device Vil and Vih. At slew rates below this, the device inputs become
extremely sensitive to signaling, ground, power and device noise.
No DRAM manufacturer wants to even touch specifications below
these slew rates, especially when the non-monotonic input behavior
occurs between Vil and Vih. Or for new devices, Vachigh and Vaclow.

Physically the receiver is an amplifier without hysteresis. It is extremely
senstive and has a high gain bandwidth product (i.e. high bandwidth).
A non-monotonic glitch in the threshold region (which at any point in space,
time,
process and temperature is someVoltage +/- 25 mV) can cause the
amplifier to switch if there is enough energy in the glitch, which is
related to
it's frequency and the amplifier's bandwidth. The higher the bandwidth of
the
amplifier (faster switching time) the more sensitive. So, a glitch in the
edge can cause several pulses, or even runt pulses to be passed from the
input receiver to subsequent latches in the devices. These device latches
do not have any additional stages to reduce the probability of metastability
events. (Remember this is "synchronous memory.) They drive almost
directly into the device column and row amplifiers of the array which is not
a good place meta stable events to occur.

As devices become faster these problems become more pronounced and
more likely. Take a look at the specifications for Intel GTL receiver
timing.
They went to pains to describe a way of derating timing for non-ideal
inputs.
There's no major difference between these receivers than those on other
devices like memory. With Vil and Vih of 800mV and 2000 mV, there is
room for margin ... if we use Vil and Vih as the receiver timing thresholds.
However, compared to the nominal switch point of about 1400 mV there
is a big difference in the timing numbers that one would see in simulation
or
in measurement. If you derate all timings to Vil and Vih ... which by the
way are not the stated timing measurement points for SDRAM ... then you
lose lots-o-timing. Unfortunately, if you have ill-behaved waveforms at
device inputs, then you can have some terribly degenerate behavior at the
receivers ... and some bad stuff can happen inside of these devices ... even
within the Vil and Vih limits.

regards,

scott

"Peterson, James F (FL51)" wrote:

> Regarding non-monotonic edges on SDRAM :
> I have also heard that SDRAMs are very sensitive to this problem. I don't
> think the responses so far have completely explained why a non-monotonic
> edge on an address line can cause a problem in synchronous memory.
> Does anyone have a good explanation for why this occurs?
> thanks,
> Jim
> Jim Peterson
> jfpeterson@space.honeywell.com
> Honeywell, Space Systems Division, M/S 934-5
> 13350 US 19 N., Clearwater, FL, 34624
> 727-539-2719
>
> -----Original Message-----
> From: Netzler Dirk [mailto:Dirk.Netzler@icn.siemens.de]
> Sent: Friday, February 11, 2000 2:02 AM
> To: 'si-list@silab.eng.sun.com'
> Subject: [SI-LIST] : montonic signals at SDRAM-, SSRAM- and
> FEPROM-adress inputs
>
> Hello All,
>
> every time I have to design memory buses I wonder wether signals at adress
> inputs
> of synchronous memory chips (SDRAM, SSRAM) ) must have monotonic edges or
> not.
> If yes, can anybody give me an explanation for that ?
>
> And what's about FEPROMs ? Okay, the control signals (e.g. WE,OE) need to
be
> monotonic.
> But what's about the adress inputs ? Should they be monotonic, too ? I
don't
> find reasons for that.
>
> What are your experiences ?
>
> Best regards
>
> Dirk Netzler
> Siemens AG
>
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--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com

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