From: Dan Irish (Dan.Irish@east.sun.com)
Date: Fri Mar 24 2000 - 09:41:54 PST
I would say that, as long as clocks and continuous signals
(e.g. Fibre Channel) were buried on the inner signal layers
in stackup #2 (S-P-S-S-G-S,) that flooding the rest of these
signal layers would give some benefit from buried capacitance.
I assume that you would flood the signal layer next to G with P,
and flood the signal layer next to P with G.
Burying the clocks is an important condition--I would
say that the reduction in EMI from burying the clocks far
outweighs the benefits of buried capacitance of
a S-G-P-P-G-S stackup.
I would stitch the perimeter of the flooded areas
to the P and G layers, too.
It used to be that mixing signals and shapes (especially shapes
inside of shapes) was difficult to do with some PCB layout
software (i.e. our supplier's.) I think this is easier to do now.
I'm no fab expert, but I believe adequate spacing (~25 mils)
is needed between signals and shapes for consistent etching.
Also, these mixed layers should have the same amount of flooding
on both layers. Otherwise, I believe warping can result
If done carefully, I think flooding is a good idea.
This is done a lot with inexpensive (2-layer and 4-layer)
> Date: Fri, 17 Mar 2000 12:59:06 -0800
> From: Lawrence Butcher <Lawrence.Butcher@eng.sun.com>
> MIME-Version: 1.0
> To: email@example.com
> Subject: [SI-LIST] : Fun With Stackups again
> Content-Transfer-Encoding: 7bit
> A question about 1) S-S-P-G-S-S vs 2) S-P-S-S-G-S stackup.
> I have often wondered whether it would be a good idea to use
> 2) above, but to use all available space on the inner S layers
> as additional P and G layers.
> Assuming that a large fraction of the inner layers were avaialable,
> and that the board could be swiss-cheesed with vias, the stackup
> would look like S-P-G-P-G-S.
> Unfortunately there is large spacing between the internal power and
> ground layers.
> Is this a half-way step which might behave well at low frequencies
> due to buried traces, and well at high frequencies due to the
> higher buried capacitance?
> Even in the case of 1), should we be using all available unused
> routing layers as additional buried capacitance?
> This could be a "simple" post-routing step in the PCB design process.
> It could be applied to boards with any stackup.
> It might make it fun to try to run constant-impedance traces around
> the board, though. We would have to keep our eyes on changing
> geometries and complicated return current paths.
> **** To unsubscribe from si-list or si-list-digest: send e-mail to
firstname.lastname@example.org. In the BODY of message put: UNSUBSCRIBE
UNSUBSCRIBE si-list-digest, for more help, put HELP.
> si-list archives are accessible at http://www.qsl.net/wb6tpu
**** To unsubscribe from si-list or si-list-digest: send e-mail to email@example.com. In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
This archive was generated by hypermail 2b29 : Thu Apr 20 2000 - 11:35:53 PDT