RE: [SI-LIST] : Fast edges with limited plane capacitance

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From: jrbarnes@lexmark.com
Date: Mon Mar 20 2000 - 08:49:40 PST


Matt,
I also prefer s1-G-s2-s3-P-s4 for a six-layer card. Active components go on s1.
Depending on board density and the kinds of passive components needed, passive
components go on s1 or s4. We have achieved 71-76 ohm transmission-line
impedance (Zo) in all signal layers of a six-layer card using:
* 0.006" lines and spaces.
* 2 ounce/foot^2 copper topside and bottomside.
* 1 ounce/foot^2 copper for inner layers.
* 0.007"/0.013"/0.013"/0.013"/0.007" FR-4 laminations .

The highest-speed signals are routed on signal layers s1 and s2, using the
ground plane G as their reference. G is solid, having only holes for anti-vias
(clearance holes for vias that don't go to the plane) in it, and we limit the
size of these anti-vias (in G and power plane P) so that they don't create long
slots even under pin-grid-array (PGA) parts and dense connectors. Clocks and
other critical signals (fast rise-/fall-times and high frequencies) are routed
on s2 as much as possible, but on both s1 and s2 we encircle the clock signal
with a guard trace, creating ground-signal-ground to minimize the loop area.
The guard trace is connected to ground pins at the driving and receiving IC's,
and a via carries the guard trace between layers anywhere the clock signal
changes layers.

Slower-speed signals are routed on signal layers s3 and s4, using power plane P
as their reference. If P has to be segmented into different voltages, we stitch
the pieces together with 100nF surface-mount capacitors (initial guess, at
least) about every 0.5" anywhere signals on s3 or s4 have to cross the moats.

We also put ground traces wherever we can on each layer, and tie them together
with vias, to create dense ground-grids in addition to the ground plane. Then
we use ground infill to fill as much of each layer as we can with copper. After
ground infill, if a ground patch on any layer has only one connection and is
bigger than about 0.5" x 0.25", I run one or more additional ground wires or
vias to it to take advantage of it as another return-current path and to keep it
from acting like a patch antenna.

I put a narrow ground ring on P, all the way around the card. I also ring every
layer with ground, and tie this six-layer "Faraday cage" together with vias
about every 0.5" (irregularly spaced). This way I don't have to worry about
radiated fields radiating from the power plane if I manage to excite it at high
frequencies. I also put extra 100nF capacitors between power and ground around
the entire periphery of the card, about 1" apart in areas where I don't have
bypass capacitors for active components. Inner areas of the card that don't
have active components also get 100nF bypass capacitors on a roughly 1" x 1"
grid, to help tie G and P together for signals that have to change from s1/s2 to
s3/s4.

I split ground into two nets: digital ground and front-end ground. Front-end
ground is a wide strip in all layers along the edge that has connectors to the
outside world. The bodies of metal-cased connectors go to front-end ground
along with the mounting pads for the metal bracket that holds the connectors.
The moat between front-end ground and digital-ground/power/signals is the same
in all layers to minimize capacitive coupling. The front-end ground is
narrowed to 0.1" if necessary to permit signals to reach connector pins without
crossing it. This leaves enough width that we can tie all six layers of
front-end ground together with vias every 0.5" or so and still leave a solid
face of copper to the outside world. Front-end ground is tied to digital ground
with narrow straps on the s1 and s4 layers near the mounting pads for the metal
bracket and about every 2-3" across the width between connectors. This way, if
we want, we can easily separate front-end ground from digital ground during
Radiated Emission tests to see if it helps us. (So far we have always had the
best results with front-end ground tied to digital ground, but I like having
some "wiggle room".)

If at all possible, we put the passive components associated with a crystal or
phase-locked loop (PLL) on the s1 layer. Keeping them close to the integrated
circuit pins, with short fat traces (length-to-width under 3:1 if possible)
close together, keeps the loop area extremely small. We put solid ground under
the crystal itself on s1 to reduce jitter, and try not to route any signals
under the crystal or its traces if we can help it. At the very least, signal
traces in layers s2, s3, or s4 have at least two layers of ground to guard them
from the crystal. The components for a PLL loop filter will go on s1 if
possible, or on s1 and s4 if that makes the layout much more compact. We cut a
"Hardin C", a moat around these components and signals in all layers of the card
with a bridge just wide enough for the PLL's signal pins and ground pin. We
infill the inside of this moat with ground on all layers, and add vias in ground
around its periphery, to create a Faraday cage that is referenced to the PLL's
ground pin. This minimizes jitter from signals/return currents passing near the
PLL.

The front-ends of Local Area Network (LAN) interfaces get common-mode chokes to
keep the LAN cables from acting as antennas. We keep all layers clear of
copper, except for the transmit/receive traces themselves, from the magnetics to
the connector to prevent capacitive coupling to the LAN cables. Other signals
to the magnetics/ connector are routed around the clear area as much as possible
with just the minimum necessary length in the clear area, and kept as far away
from the transmit/receive traces as possible. No foreign signals are permitted
to encroach upon or cross this clear area, even if routing them around the clear
area adds a couple of inches to their length. And if possible, we also have a
ground trace terminated at both ends separating any foreign signals from the
clear area.

                                   John Barnes Advisory Engineer
                                   Lexmark International
                                   author of Electronic System Design:
                                       Interference and Noise Control Techniques
                                       (Prentice-Hall, 1987)

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