Re: [SI-LIST] : 10 layer board stackup

About this list Date view Thread view Subject view Author view

From: Lee Ritchey (leeritchey@earthlink.net)
Date: Thu Jan 20 2000 - 17:48:48 PST


My experience with problems like this has been that the emissions are getting off the PCB on some unshielded wire or wires. As long as the power planes
are continuous from side to side (you didn't mention how solid the power planes are) clock traces on outer layers don't emit enough energy to fail, even
CISPRB. So, if you just add more layers and "bury" the clocks, you are likely to still fail, and in the bargain, the PCB will cost more.

Can you supply information on whether or not any of the power planes (ground or Vcc) are split or have sections removed and what kinds of wires are leaving
the PCB? That will be useful information on how to diagnose the problem. Just adding layers, may not do it.

Lee

kogler@earthlink.net wrote:

> I presently have an 8 layer board as follows:
>
> sig top
> grd
> pwr
> internal 1
> internal 2
> pwr
> grd
> sig bottom
>
> We failed radiated emissions. All clock/fast signals were routed on
> surface of board - since system is battery operated, ie keep the power
> consumption down. Routing these signals on inner layers will draw more
> power? Since we failed radiated emissions miserably, the plan is to now
> bury the clock signals on the inner layers. Emissions exceeded - out to
> 7th harmonic of clocks (19.66MHz - from which the following clocks are
> generated, 117.96MHz, 58.9824Mhz, and 29.4912MHz) Three other clocks
> are
> at 32.514MHz, 12.000MHz, and 24.576MHz. We are adding damping
> resistors.
> We are also adding 2 more signal layers to the board for the clock/fast
> signals - impossible to route clock signals on either internal 1 or 2,
> also under a time crunch. I am looking for advise on the board stackup
> for this now 10 layer board.
>
> Stackup as planned
>
> Sig top
> grd
> pwr 3.3V
> new layer for clocks/fast edge rates/repetitive
> internal 1
> internal 2
> new layer for clocks/fast edge rates/repetitive
> pwr 5V
> grd
> sig bottom
>
> Also checking into smaller decoupling capacitors - higher self-resonant
> frequency - presently my board has all decoupling capacitors with 0.1uF
> values.
>
> I have seen 10 layer stackups with pwr and grd layers separated by as
> many
> as 6 layers. I want to keep the pwr and grd layers close in my
> application
> for good board decoupling.
>
> Please email me at rwkinney@ra.rockwell.com as I will be offsite from my
> office for the next couple of weeks.
>
> Regards,
>
> Gary Steinkogler
>
> **** To unsubscribe from si-list: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP.
> si-list archives are accessible at http://www.qsl.net/wb6tpu
> ****

**** To unsubscribe from si-list: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
****


About this list Date view Thread view Subject view Author view

This archive was generated by hypermail 2b29 : Thu Apr 20 2000 - 11:34:46 PDT