RE: [SI-LIST] : Signal traces without reference plane

About this list Date view Thread view Subject view Author view

From: Stephanie Goedecke (stephanie.k.goedecke@exgate.tek.com)
Date: Mon Jan 10 2000 - 10:57:22 PST


My experience is that your concerns can be real and depend mostly
on the distances and edge rates involved. For your top signal,
the "some impedance mismatch" can degrade the signal fatally,
depending on the particular set-up. If you have this situation in
a real layout, I suggest you do a signal analysis on the board
before you have the board built.

How relevant is this theory to actual PCB design? I don't know.
How relevant is it if your board works?

-Stephanie

-----Original Message-----
From: Heiko Dudek [mailto:heikod@cadence.com]
Sent: Wednesday, November 17, 1999 8:45 AM
To: si-list@silab.eng.sun.com
Cc: hans.betz@abg1.siemens.de
Subject: [SI-LIST] : Signal traces without reference plane

Hi,

since being involved in a discussion about "routing pcb traces while
having
partially no ground reference", I would love to get some other opinions.
So,

assume a setup like this:
(Which you can get on systems with multiple GND / VCC potentials
easily.)

 ______________________
                       |
       GND Plane |
                       |
 ________________________________
 (<-Receiver) Signal Trace |
 ____________________________ |
                       | | |
                       | | |
                       | | |
                       | | |
 ____________________________| |
 (<-Driver) |
 ________________________________|
                       |
 _____________________ |
  Second Signal Trace ||
 __________________ ||
                   | ||
                   | ||
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
                   

Theoretically I would expect some differential mode EMI because of the
current loop the return current on the ground plane forms with the
signal current.
Of course, there's some reflection on the signal trace because of the
impedance mismatch; additionally one should see some additional
inductance because of
the E field stretching (which goes along with H concentrating) serial to
the
signal trace. Finally, there might be some coupling into the second
signal trace.

The *BIG* question is, how relevant is this theory (if applicable at
all) to
actual PCB design ? What are your experiences on this ? How do you
control
(or better, avoid) this configuration while autorouting ? Do you care at
all (if
yes, what's the critical edge rate you have to start worrying) ?

Thank you very much,

Hans Betz
Heiko Dudek

**** To unsubscribe from si-list: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list
****


About this list Date view Thread view Subject view Author view

This archive was generated by hypermail 2b29 : Thu Apr 20 2000 - 11:34:31 PDT