# RE: [SI-LIST] : interplanar capacitance

From: Greim, Michael ([email protected])
Date: Thu Feb 03 2000 - 12:56:49 PST

Hi Ewart,

First of all, if you have the opportunity, you might want to
modify your stack up to have an even greater amount of
interplane capacitance. By routing your signals as ortho-
gonal pairs on the inner layers, you should be able to
keep your coupling down to the point where you don't have
any problems with it. Here is the stack up:

Primary Side
+ 5V plane
GND plane
Internal Signal 1 (x direction)
Internal Signal 2 (y direction)
+3.3 V plane
GND plane
Secondary side

Remember that a circuit board is made up of alternating
very expensive due to the dimensional instability as the
material thins (low yield). Thin prepreg on the other hand
is relatively inexpensive. In fact using very thin prepreg
(say 2 mil) may allow you to use even thicker clad FR4
that could again help increase yield. If you put your thin
prepreg cores between the power planes, you can see

Interplane capacitance is defined as follows:

C = (0.225 * Er * A)/D

A is the plane area in sq in.
D is the distance between planes

With a two mil separation between planes you will rea-
lize roughly 500 pf per square inch with very low inductance.

Another technique that you might like to try is called
plane filling. Essentially, you use the above technique
to create other capacitors on the signal layer. Why allow
the fab shop to perform thieving when you can do essentially
the same thing and improve your power systems high
frequency response. Remember to alternate your power
and grounds as you will also be coupling to the adjacent
power plane. Remember to be careful when doing this
as you can change your trace impedance and cause
undesireable behaviour.

Best Regards,

Michael

> -----Original Message-----
> From: Speer, Ewart [SMTP:[email protected]]
> Sent: Thursday, February 03, 2000 2:49 PM
> To: '[email protected]'
> Subject: [SI-LIST] : interplanar capacitance
>
> Dear List Members,
>
> I have an eight layer board with four routing and four plane layers. The
> stackup I have chosen is;
>
> Primary side (signal) - contains all components
> +5V (full plane)
> Internal (signal)
> GND (full plane)
> +3.3V (full plane)
> Internal (signal)
> GND (full plane)
> Secondary side (signal) - no components
>
> I want to take advantage of the interplanar capacitance between planes GND
> and +3.3V. What core thickness should I specify? At what dimension
> (thickness of core) would I lose this advantage? Also, on the secondary
> side under an FPGA I have a large copper fill area that carries +2.5V, can
> I use the adjacent GND plane and this area fill for more decoupling. If
> so what thickness of prepreg should I specify? I would like to maintain a
> 0.062" overall thickness of the PWB.
>
> Thank you all,
> Ewart Speer
> Scientific Atlanta
>

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