Re: [SI-LIST] : on-chip decoupling capacitance

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From: bgrossma (bgrossma@td2cad.intel.com)
Date: Wed Apr 12 2000 - 16:43:23 PDT


Chris,

Unfortunately I don't have published resource w.r.t how much on-chip
power supply decoupling capacitance is suggested, we do attempt to push
certian 'guidelines' on our product groups to help us meet our wafer
test (sort) requirements. In our case, relatively large inductance
between the chip and the nearest off-chip decaps limits the
effectiveness of these caps to respond to fast, transient activity.
Based on the knowledge of our environment, and what we understand of the
chip we try and provide truly useful guidelines like "You guys better
put enough decap on die to support the first X nS of droop, or I'll be
mad". Of course if I had my way I would ask for a two tons of the on-die
stuff, but that would increase the die size to about 1 die/wafer which
is not too good for yield.

In a nutshell, the decoupling placed on board for us doesn't even see
the initial transient activity, the on-die decoupling has to be able to
manage that. It may be an option of put on more on-die stuff, or slow
down the clock at sort, this option would generally be frowned on by the
market.

Not really a new concern either, we've had to worry about it in my
little niche of the world for at least the last 5 years - before that I
just can't say (it wasn't my niche then).

It's been a few years since I was in the chip design arena, but there
used to be some decent newsgroups (forgive my memory but something like
cad.vlsi.? ). For text's, most VLSI design textbooks (at least from 5 or
so years back) used to devote a very small section to on-chip power
supply noise (you probably would have to dig for it) and they would
generally list references that you could follow.

Best regards,

-Brett

Chris.H.Simon@gd-is.com wrote:
>
> There has been a lot of good discussion on this list about decoupling capacitance for high
> performance systems. So far, I believe, all of this discussion has been around the
> quantity and quality of capacitors mounted on the substrate. My question is in regards to
> whether this is adequate for very high speed, low voltage core logic in deep sub-micron
> chips.
> Are we at a point where the external capacitors are so far away from the core logic (i.e.,
> separated by bond wires and IC power grid routing) that something more is needed on-chip?
> (In addition to, not in place of the board caps.)
> I have heard rumors that modern microprocessors use 10s of nF of on-chip decoupling
> (presumably provided by large areas of thin oxide) to keep the core supply noise in a
> range where the flip-flops don't loose their minds.
> Can anyone on this list point me to published resources that discuss this issue and when
> I'm going to get myself into trouble? Is this a problem only for ICs using dynamic logic
> which may be more noise sensitive? I'm doing my first 0.25 um design and I'm beginning to
> understand some of the on-chip SI issues, but this is one I haven't heard much about.
>
> Does anyone know of a similar email reflector that deals with chip design issues such as
> this, or are we SI guys the only ones lucky enough to have a Ray Anderson to set something
> like this up?
>
> Chris Simon
> Electrical Engineer
> General Dynamics Information Systems
>
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