si-list.mail by subject
Starting: Sun 03 Jan 1999 - 10:51:45 PDT
Ending: Wed 20 Oct 1999 - 10:53:47 PDT
Messages: 1959
- (2) Positive ECL (PECL) voltage swings,
- (2) Positive ECL (PECL) voltage swings, but d
- (2) Positive ECL (PECL) voltage swings, but designed
- =?iso-8859-1?Q?RE=3A_=5BSI=2DLIST=5D_=3A_IBIS_Subcommittee_For?=
- [Fwd: [SI-LIST] : EMC on large distributed systems]
- [SI-LIST] : "Best" way to ground board?
- [SI-LIST] : "Damn Fast" buffer
- [SI-LIST] : "Picket Fence" (Via Fence) for increasing
- [SI-LIST] : "Picket Fence" (Via Fence) for increasing isolation
- [SI-LIST] : "Reply To:" Survey Results
- [SI-LIST] : "Spread Spectrum Clock Techniques" talk in Santa Clara CA
- [SI-LIST] : 1 GHz probe plans posted
- [SI-LIST] : 2.5 Gb/s for Gigabit Ethernet with Vitesse VSC7146
- [SI-LIST] : 20-H Rule for Power Planes
- [SI-LIST] : 2000 International Symposium on Quality of Electronic Design
- [SI-LIST] : 3rd International IEEE Workshop "Signal Propagation on Interconnects"
- [SI-LIST] : 8b/10b
- [SI-LIST] : =?ISO-8859-1?Q?RE=3A_=5BSI-LIST=5D_=3A_AMPredictor=AE_Signal_I?=
- [SI-LIST] : [SI-LIST] Positive ECL (PECL) voltage swings,
- [SI-LIST] : [SI-LIST] Positive ECL (PECL) voltage swings, but
- [SI-LIST] : [SI-LIST] Positive ECL (PECL) voltage swings, but designed to be
- [SI-LIST] : [SI-LIST]:Drivers to minimize reflections
- [SI-LIST] : A Question About Power Noise.
- [SI-LIST] : About HSPICE model
- [SI-LIST] : About the AC analysis with HSPICE
- [SI-LIST] : About the AC signals SI analyse
- [SI-LIST] : About the eye pattern of high speed backplane
- [SI-LIST] : About the Eye Patterns and the terminations of bus
- [SI-LIST] : Accuracy of Hspice's W element
- [SI-LIST] : Acronyms
- [SI-LIST] : acronyms........SSTL
- [SI-LIST] : Advice for long bus?
- [SI-LIST] : agc amplifier
- [SI-LIST] : AGENDA - EUROPEAN IBIS SUMMIT MEETING
- [SI-LIST] : AMPredictor=?iso-8859-1?Q?=AE_Signal_Integrity_Analyzer_(SIA)?=
- [SI-LIST] : An Interesting Presentation
- [SI-LIST] : Another online simulation
- [SI-LIST] : Any Veribest SI tool experiences?
- [SI-LIST] : Anyone doing SI simulations for Pentium
- [SI-LIST] : Anyone doing SI simulations for Pentium II
- [SI-LIST] : Anyone doing SI simulations for Pentium II boards?
- [SI-LIST] : Anyone doing SI simulations for Pentium IIboards?
- [SI-LIST] : Anyone interested in PCB Design Techniques for SI & EMC?
- [SI-LIST] : Anyone interested in PCB Design Techniques for SI & EMC? -----Original Message-----
- [SI-LIST] : Anyone interested in PCB Design Techniques for SI& EMC?
- [SI-LIST] : Asymmetric Striplines Configuration
- [SI-LIST] : Atomic animation
- [SI-LIST] : Automatic/Semi-automatic design check of PCB
- [SI-LIST] : Automatic/Semi-automatic design check of PCB layout database for
- [SI-LIST] : Automatic/Semi-automatic design check of PCB layout database for crosstalk/SI viol
- [SI-LIST] : Automatic/Semi-automatic design check of PCB layout database for crosstalk/SI violat
- [SI-LIST] : backside metal
- [SI-LIST] : Best type of models, edge rates & load
- [SI-LIST] : BGA pin location
- [SI-LIST] : BGA socket modeling
- [SI-LIST] : BGA vs Leaded - summary
- [SI-LIST] : BGA vs Leaded package electrical performance
- [SI-LIST] : Bonding options to short Busses on a die
- [SI-LIST] : Book for sale
- [SI-LIST] : Broadside Coupled Traces
- [SI-LIST] : BTE models
- [SI-LIST] : Buffer Delay Vs Timing_location parameter in IBIS
- [SI-LIST] : buried capacitance vendors?
- [SI-LIST] : Call for presentations, 3-D packaging advanced technology worksho
- [SI-LIST] : Call for presentations, 3-D packaging advanced technology workshop
- [SI-LIST] : Capacitance in a Ceramic changes
- [SI-LIST] : Capacitance in a Ceramic changes ?i usedf
- [SI-LIST] : CBT for Signal Integrity
- [SI-LIST] : Chip level Vs Board level SI
- [SI-LIST] : Clarification on the current issues on Hspice W-element
- [SI-LIST] : Clock Skew Measurements
- [SI-LIST] : Clue-by-four (was OVERSHOOT ... RATING)
- [SI-LIST] : coming up with average power estimates for
- [SI-LIST] : coming up with average power estimates for buffers
- [SI-LIST] : Complex Math examples?
- [SI-LIST] : Conference Announcement - VLSI'99: Xth IFIP Conference on VLSI
- [SI-LIST] : connector substitution for high speed signals
- [SI-LIST] : Consulting on SI issues
- [SI-LIST] : Critical Length
- [SI-LIST] : Cross hatched ground planes
- [SI-LIST] : Cross hatched planes
- [SI-LIST] : Current probe EMC paper posted (finally)
- [SI-LIST] : Current-steering output design references
- [SI-LIST] : DDR Synchronous DRAM - Samsung Semiconductor
- [SI-LIST] : DDR-SDRAM specification Location
- [SI-LIST] : Dear XTAL expert...
- [SI-LIST] : Decoupling caps and power plane effects
- [SI-LIST] : Decoupling strategy in tight spaces
- [SI-LIST] : dielectric losses vs skin effect losses
- [SI-LIST] : Different board vendors different impedances
- [SI-LIST] : Different IBIS question
- [SI-LIST] : Different oz copper for grounds
- [SI-LIST] : Differential clock jitter and switching noise
- [SI-LIST] : differential pair routing
- [SI-LIST] : Differential pairs and place splits
- [SI-LIST] : differential signals
- [SI-LIST] : Differential Transmission Lines
- [SI-LIST] : Director, Package Characterization
- [SI-LIST] : Distinguishing Differential Models
- [SI-LIST] : Down-bond in chip packaging
- [SI-LIST] : driving a 300pF load
- [SI-LIST] : Duplicate Messages
- [SI-LIST] : Earth Ground
- [SI-LIST] : ECL prescaler
- [SI-LIST] : Edge rates
- [SI-LIST] : edge-rates and vias
- [SI-LIST] : Effect of low Zo for unterminated lines
- [SI-LIST] : EIAJ is mulling over a more accurate Spice model
- [SI-LIST] : Embedded Decoupling - The next Step in PWB Design
- [SI-LIST] : EMC at low frequencies
- [SI-LIST] : EMC on large distributed systems
- [SI-LIST] : EMC presentation in Orange County
- [SI-LIST] : EMC quiet serial device: Followup???
- [SI-LIST] : EMC quiet serial device???
- [SI-LIST] : EMC Training
- [SI-LIST] : EMC&FCC issues
- [SI-LIST] : EMI consultant?
- [SI-LIST] : EPEP '99 Final Program
- [SI-LIST] : Error in my timing-101 presentation
- [SI-LIST] : ESD Gun
- [SI-LIST] : Estimating DIMM Power Consumption
- [SI-LIST] : Estimating the Inrush current
- [SI-LIST] : EUROPEAN IBIS SUMMIT MEETING REMINDER
- [SI-LIST] : even-odd mode influence
- [SI-LIST] : even-odd mode influence
- [SI-LIST] : Exciting Opening at Sun-Menlo Park, CA
- [SI-LIST] : Exciting SI opening at EMC
- [SI-LIST] : eye diagram demo from Avanti
- [SI-LIST] : Eye diagram displays from HSPICE simulations
- [SI-LIST] : eye pattern definition
- [SI-LIST] : Fast Semiconductors
- [SI-LIST] : FCAL data pattern
- [SI-LIST] : Features to look for in an SI Tool
- [SI-LIST] : Ferrite Bead models
- [SI-LIST] : Fibre Channel
- [SI-LIST] : Final CFP for ISQED 2000
- [SI-LIST] : Flat Ribbon Cable substitutes
- [SI-LIST] : Flatpanel VGA questions
- [SI-LIST] : Flexible and Passive PCI Backplane?
- [SI-LIST] : fork, endfork and more fork
- [SI-LIST] : FPC impedance control
- [SI-LIST] : FR-4 and PCB Tolerances
- [SI-LIST] : Future I/O Physical or Cable Requirements
- [SI-LIST] : FW: Information on Connector Company IPEX?
- [SI-LIST] : FW: Seeking information about heatsink.
- [SI-LIST] : FYI ieee salary survey results
- [SI-LIST] : GBIC evaluation kit
- [SI-LIST] : Gentle Reminder Time Again
- [SI-LIST] : Geometry-Transfer from I-DEAS to EMAS
- [SI-LIST] : GHz Op Amps
- [SI-LIST] : Gigabit testing standards and methods wanted
- [SI-LIST] : GND on the outer layers
- [SI-LIST] : Ground gap problem
- [SI-LIST] : Grounding & Shielding: Coupling Vs Radiation
- [SI-LIST] : Guard trace question
- [SI-LIST] : Handy little models
- [SI-LIST] : HAPPY99 virus DONOT click it...
- [SI-LIST] : High frequency decoupling Capacitors
- [SI-LIST] : High signal density controlled impedance connectors
- [SI-LIST] : High speed design guides available ?
- [SI-LIST] : high-power board
- [SI-LIST] : How board over-shoot under-shoot influence a
- [SI-LIST] : How board over-shoot under-shoot influence a chip.
- [SI-LIST] : How do you use buried capacitance?
- [SI-LIST] : How to decouple POWER/GND , heavy current backplane
- [SI-LIST] : How to find a way to solute the double-side PCB design quality
- [SI-LIST] : How to simulate the jitter of the part?
- [SI-LIST] : How to treat the ASIC package pin-assigns
- [SI-LIST] : Howard Johnson Presentation
- [SI-LIST] : HP-ADS
- [SI-LIST] : Hspice analysis of IBIS model
- [SI-LIST] : HSPICE lossy w element
- [SI-LIST] : HSPICE schematic entry and simulation interface
- [SI-LIST] : HSTL
- [SI-LIST] : HSTL voltage levels
- [SI-LIST] : Hyperlinx
- [SI-LIST] : I/O technologies and live insertion
- [SI-LIST] : IBIS Accuracy Specification First Draft
- [SI-LIST] : IBIS Model for Hitachi 64M SDRAM
- [SI-LIST] : IBIS Model Libraries
- [SI-LIST] : IBIS Modeling Info Requested
- [SI-LIST] : Ibis models
- [SI-LIST] : IBIS Models for Micron 1Mb Syncburst SRAM
- [SI-LIST] : IBIS models for oscillators - ??
- [SI-LIST] : IBIS models, how to fill in the missing pin info and other.
- [SI-LIST] : IBIS simulation of ZBT SRAM
- [SI-LIST] : IBIS Subcommittee Formed to Review Spice to
- [SI-LIST] : IBIS Subcommittee Formed to Review Spice to IBIS
- [SI-LIST] : IBIS Subcommittee Formed to Review Spice to IBIS
- [SI-LIST] : IBIS Subcommittee Formed to Review Spice to IBIS
- [SI-LIST] : IBIS Subcommittee Requests Input Regarding S2IBIS2
- [SI-LIST] : IBIS SUMMIT - October 14, 1999 -
- [SI-LIST] : IBIS Summit - Thursday, 14-Oct-99 - AGENDA included
- [SI-LIST] : IBIS to SPICE
- [SI-LIST] : IC impedance
- [SI-LIST] : IDE bus question
- [SI-LIST] : Idsat variation
- [SI-LIST] : IEEE Paper
- [SI-LIST] : IMAPS Presentation on Simulating Fibre Channel Loss
- [SI-LIST] : IMAPS Presentation on Simulating Fibre Channel Loss
- [SI-LIST] : Improved online decoupling model
- [SI-LIST] : Intel apparenly has found the Rambus problem on the 820
- [SI-LIST] : Intel apparenly has found the Rambus problem on the 820 (Camino)
- [SI-LIST] : Interconnect Coupling capacitance
- [SI-LIST] : Interconnect modeling from measurements
- [SI-LIST] : Interconnect modeling from TDR measurements
- [SI-LIST] : internal series resistors
- [SI-LIST] : Introduction to Transmission Lines
- [SI-LIST] : It's Spring in Texas!
- [SI-LIST] : Jitter
- [SI-LIST] : Jitter book
- [SI-LIST] : Jitter book found
- [SI-LIST] : Job Opening
- [SI-LIST] : Job Opening -- IBM Corporation, Poughkeepsie NY
- [SI-LIST] : Job Openings at Intel in Santa Clara
- [SI-LIST] : Job Opportunity at Amkor Technology
- [SI-LIST] : Job Posting
- [SI-LIST] : Job Posting - Mayo Foundation in Minnesota
- [SI-LIST] : Job posting: Ansoft Corporation
- [SI-LIST] : Job posting: Motorola
- [SI-LIST] : limitations of spice for SI modelling
- [SI-LIST] : Logic, Circuit, and Physical Designers wanted
- [SI-LIST] : Long bus, terminate or star?
- [SI-LIST] : Long, uni-dir bus with multiple loads termination
- [SI-LIST] : Looking for a sensitive Gigabit receiver part
- [SI-LIST] : Looking for good resources on SSTL transmission and termination..
- [SI-LIST] : looking for info on Hspice vs Star-Sim comparison
- [SI-LIST] : Looking for Intel 82440GX chipset IBIS model
- [SI-LIST] : Looking for Recommendations
- [SI-LIST] : looking for signal integrity engineer position
- [SI-LIST] : Looking Inside IBIS Model
- [SI-LIST] : Looking inside the IBIS model
- [SI-LIST] : low jitter PLL ?
- [SI-LIST] : Low Voltage CMOS question
- [SI-LIST] : LVDS to Differential LVPECL conversion?
- [SI-LIST] : LVDS-to-ECL and vice versa
- [SI-LIST] : LVDS-to-PECL and vice versa
- [SI-LIST] : LVTTL Drivers vs. LS
- [SI-LIST] : Macro modeling of Buffer
- [SI-LIST] : Magnetic Field Immunity
- [SI-LIST] : Magnetic field probe paper posted
- [SI-LIST] : mail list subject
- [SI-LIST] : Materials from MMontrose PCB Design Techniqu
- [SI-LIST] : Materials from MMontrose PCB Design Techniques for SI & EMC
- [SI-LIST] : Measuring noise with Differntial probe
- [SI-LIST] : Meeting, Boston area, Power Distribution and Performance
- [SI-LIST] : Memory Burn-In Board & Driver's Characteristics
- [SI-LIST] : METASTABILITY IN FLIP FLOPS
- [SI-LIST] : MG Interconnectix
- [SI-LIST] : micro BGA SI vrs PCB consideration
- [SI-LIST] : Microstrip losses
- [SI-LIST] : mini co-ax
- [SI-LIST] : Mini-coaxial cable
- [SI-LIST] : minimizing backplane clock jitter
- [SI-LIST] : Missing Person
- [SI-LIST] : Mixing GTLP Tx with GTL Rx
- [SI-LIST] : Modeling Package parasitics
- [SI-LIST] : Modeling Package parasitics (measurements)
- [SI-LIST] : Modeling power noise
- [SI-LIST] : Modification of decoupling-caps
- [SI-LIST] : Moment Method/Ensemble/Touchstone/Errors
- [SI-LIST] : Mutual capacitamce and inductance
- [SI-LIST] : Mutual capacitance and inductance
- [SI-LIST] : Mux. of clock sources
- [SI-LIST] : Need Information on effect of 45 degree angles on high
- [SI-LIST] : Need Information on effect of 45 degree angles on high speed sign
- [SI-LIST] : Need Information on effect of 45 degree angles on high speed signals.
- [SI-LIST] : Need information on inexpensive Circuit
- [SI-LIST] : Need information on inexpensive Circuit simulation tools
- [SI-LIST] : Network analysis references for PEEC technique
- [SI-LIST] : Noise Voltage levels vs. EMI levels
- [SI-LIST] : Non-standard bus termination (2nd posting)
- [SI-LIST] : Non-technical question
- [SI-LIST] : Nvidia hiring Signal integrity engineers
- [SI-LIST] : Of thermal reliefs and signal integrity......
- [SI-LIST] : Of thermal reliefs and signal integrity....
- [SI-LIST] : Online crosstalk simulation
- [SI-LIST] : Online Tools and Articles
- [SI-LIST] : Opamp spice model
- [SI-LIST] : Opportunity at Dell
- [SI-LIST] : Oscillation in lumped circuits and
- [SI-LIST] : Oscillation in lumped circuits and transmi
- [SI-LIST] : Oscillation in lumped circuits and transmission l
- [SI-LIST] : Oscillation in lumped circuits and transmission l ines
- [SI-LIST] : Oscillation in lumped circuits and transmission lines
- [SI-LIST] : Output Buffer Need
- [SI-LIST] : OVERSHOOT/MAX. VOLTAGE RATING
- [SI-LIST] : Package Parasitics Modelling
- [SI-LIST] : Paper on IBIS simulation algorithm
- [SI-LIST] : Parallel tracks on Flexible PCB without Ground
- [SI-LIST] : Parallel tracks on Flexible PCB without Ground Plane
- [SI-LIST] : Parallel tracks on Flexible PCB without GroundPlane
- [SI-LIST] : Pass-through vias a...
- [SI-LIST] : Pass-through vias as BGA lands
- [SI-LIST] : Pass-through vias as BGA lands (?)
- [SI-LIST] : PC100 SODIMM DRAM DQ Net Simulations
- [SI-LIST] : PCB design techniques for EMC control
- [SI-LIST] : PCB impedance variation v.s. layout pattern
- [SI-LIST] : PCB losses
- [SI-LIST] : PCB Top Gun Hall of Fame Contest -- Enter Now!!!
- [SI-LIST] : Periodic Obligatory Warning on Proprietary Postings
- [SI-LIST] : Periphery Stitching ...
- [SI-LIST] : Please stop with the 'me, too' messages.
- [SI-LIST] : Position Available
- [SI-LIST] : Position Available at Sun
- [SI-LIST] : Position available for RF simulation
- [SI-LIST] : Position Opening. Sr. Applications Engineer.
- [SI-LIST] : Position Opening. Sr. Applications Engineer. LSI Logic.
- [SI-LIST] : Positions available
- [SI-LIST] : Power Distribution along a connector
- [SI-LIST] : Power Noise
- [SI-LIST] : Power supply modeling...
- [SI-LIST] : Power supply modelling...
- [SI-LIST] : Power Supply PCB Design
- [SI-LIST] : Power/Gnd Pin Input Impedance
- [SI-LIST] : Presentation Availability for Embedded Capacitance
- [SI-LIST] : Problems with 3rd harmonics on Intel 820 Camino chipset?
- [SI-LIST] : Proposal: Rs correlation/collaboration for
- [SI-LIST] : Proposal: Rs correlation/collaboration for W-Elements
- [SI-LIST] : Proposal: Rs correlation/collaboration for W-Elem ents
- [SI-LIST] : Proposal: Rs correlation/collaboration for W-Elements
- [SI-LIST] : protection of information
- [SI-LIST] : ps-resolution
- [SI-LIST] : Q: HSPICE w-elements' RLCGs - conversion coefficients
- [SI-LIST] : Q: HSPICE w-elements' RLCGs - conversion coefficients from XFX
- [SI-LIST] : Q: HSPICE w-elements' RLCGs - conversioncoefficients
- [SI-LIST] : Q: Plane-jumping return currents
- [SI-LIST] : QUAD XTK vs. Rambus Simulation
- [SI-LIST] : Question about Multiple PWBA Ground
- [SI-LIST] : question about timing analysis
- [SI-LIST] : question about VGA signals
- [SI-LIST] : RAMBUS
- [SI-LIST] : Rambus SI problems ...
- [SI-LIST] : Rambus vs. di/dt SSN
- [SI-LIST] : RE:
- [SI-LIST] : RE: Another decoupling question
- [SI-LIST] : RE: [SI-LIST] : AMPredictor� Signal Integrity Analyzer (SIA)
- [SI-LIST] : RE: [SI-LIST]: Long bus or star?
- [SI-LIST] : RE: IBIS Subcommittee Requests Input Regarding S2IBIS2
- [SI-LIST] : RE: Long bus or star?
- [SI-LIST] : RE: Paper on IBIS simulation algorithm
- [SI-LIST] : RE: RESULTS to Proposal: Rs correlation/collaboration
- [SI-LIST] : RE: RESULTS to Proposal: Rs correlation/collaboration for W-Eleme
- [SI-LIST] : RE: SCSI IBIS models
- [SI-LIST] : RE: winmail.dat files explained- and new .zip file that can be opened
- [SI-LIST] : Recommend a CMOS/bipolar circuit design book?
- [SI-LIST] : reduce EMI from crystal oscillator ckt
- [SI-LIST] : references on leadframe and package pin materials and signal degradation
- [SI-LIST] : REMINDER TO VOTE ON IBIS SP-4557
- [SI-LIST] : Request ...
- [SI-LIST] : Resistivity of IC routing
- [SI-LIST] : Resistor Types for Terminations?
- [SI-LIST] : Resonant clocks (was:coming up with average power estimates
- [SI-LIST] : respons to semiconductor I/O edge rates
- [SI-LIST] : response to semiconductor I
- [SI-LIST] : response to semiconductor I/O edge
- [SI-LIST] : response to semiconductor I/O edge rates
- [SI-LIST] : RESULTS to Proposal: Rs correlation/collaboration for W-Elements
- [SI-LIST] : RESULTS(8/6/99) to Proposal: Rs
- [SI-LIST] : RESULTS(8/6/99) to Proposal: Rs correlation/collabora
- [SI-LIST] : return current distribution in diff pairs
- [SI-LIST] : Return Loss
- [SI-LIST] : revised 1GHz probe plans
- [SI-LIST] : RF & Digital
- [SI-LIST] : RF Design Question
- [SI-LIST] : Routing Criteria
- [SI-LIST] : Routing signals between ground and carved-up
- [SI-LIST] : Routing signals between ground and carved-up power
- [SI-LIST] : Routing signals between ground and carved-up power plane
- [SI-LIST] : Schematic entry for HSPICE
- [SI-LIST] : SCSI-LVDS Models
- [SI-LIST] : SDRAM bypassing
- [SI-LIST] : Search ? IBIS to HSPICE Tool...
- [SI-LIST] : Search for a screen capture tool
- [SI-LIST] : search for handbook
- [SI-LIST] : Searching For Equations Governing Serpentine
- [SI-LIST] : Searching For Equations Governing Serpentine Traces
- [SI-LIST] : Seeking information about heatsink.
- [SI-LIST] : Seeking Position
- [SI-LIST] : Seeking SI models for memory DIMMs.
- [SI-LIST] : Seeking Volunteer Presenters, Boston (MA,USA) area
- [SI-LIST] : Serpentine traces
- [SI-LIST] : Short Course Announcement
- [SI-LIST] : SI book available
- [SI-LIST] : SI courses
- [SI-LIST] : SI Engineer Opportunity at Huawei - Shenzhen, China
- [SI-LIST] : SI Engineer Opportunity at Huawei--Shenzhen,China
- [SI-LIST] : SI European Workshops - Amendment to Dates
- [SI-LIST] : SI job position open at Stratus in Maynard, MA ==> else delete
- [SI-LIST] : SI opening at Intel, Folsom, CA
- [SI-LIST] : SI papers for download
- [SI-LIST] : SI simulation tools
- [SI-LIST] : SI Simulations Classification
- [SI-LIST] : si-list duplicate messages
- [SI-LIST] : si-list policy on HTML postings
- [SI-LIST] : si-list posting etiquette
- [SI-LIST] : si-list Web Site Archives Update Notice
- [SI-LIST] : SI=Positions Avail
- [SI-LIST] : Signal Integrity Job Opening
- [SI-LIST] : Signal integrity on www.ChipCenter.com
- [SI-LIST] : Signal Integrity Workshops
- [SI-LIST] : Signal measurement brain teaser
- [SI-LIST] : Signal Polarities
- [SI-LIST] : signal propagation questions
- [SI-LIST] : simlifying Spice models
- [SI-LIST] : Simulating Meander Delay Lines
- [SI-LIST] : Simulation Implications of Pin and Package Parasitics
- [SI-LIST] : slides file of the IPC Boston chapter Feb 9 presentations is available
- [SI-LIST] : Slightly different signal integrity problem
- [SI-LIST] : Slotted ground planes
- [SI-LIST] : Slow falling edge of a signal.
- [SI-LIST] : SMA connector routing
- [SI-LIST] : Some Semiconductors are Unnecessarily Fast
- [SI-LIST] : source for AVX small inductance caps
- [SI-LIST] : Source of Fish Paper
- [SI-LIST] : Speakers sought for Conference on EMC Compliance
- [SI-LIST] : Speakers sought for Conference on EMC Compliance for Medical Devi
- [SI-LIST] : SPICE Training
- [SI-LIST] : split plane impact simulation
- [SI-LIST] : Spread spectrum project
- [SI-LIST] : Spreadsheet for calculation of max data transfer
- [SI-LIST] : Sr. Staff/Principal Engineer-Field Solver
- [SI-LIST] : SSTL Versus full swing PROS/CONS
- [SI-LIST] : SSTL Versus full swing PROS/CONS -- Acronyms
- [SI-LIST] : SSTL Versus full swing PROS/CONS]
- [SI-LIST] : Stackup Extraction
- [SI-LIST] : Subject: paper on Copper roughness
- [SI-LIST] : Substrate Modeling
- [SI-LIST] : T-line models & simulation
- [SI-LIST] : Tangent on Long bus or star?
- [SI-LIST] : TDR measurements
- [SI-LIST] : Tektronix IPA-510 question
- [SI-LIST] : Terminating a bi-directional bus
- [SI-LIST] : Terminating a bidirectional bus
- [SI-LIST] : Termination Examples Available?
- [SI-LIST] : Thank you for suggestions of FPC impedance control
- [SI-LIST] : Thanks Folks!
- [SI-LIST] : the old high-frequency return current model
- [SI-LIST] : The overshoot and undershoot criteria in PCI spec.
- [SI-LIST] : thick board & V/gnd microvias
- [SI-LIST] : Thin Power Plane Dielectrics
- [SI-LIST] : Trace Capacitance
- [SI-LIST] : Trace Impedance vs Supply Noise
- [SI-LIST] : Traces Impedance without plane
- [SI-LIST] : Traces Over Plane Clearances
- [SI-LIST] : Transmission Line Formulae
- [SI-LIST] : Transmission line inductance
- [SI-LIST] : Transmission line made from Parallel tracks on
- [SI-LIST] : Transmission line made from Parallel tracks on Flexible PCB
- [SI-LIST] : Transmission Line Thy Applied to short interconnects
- [SI-LIST] : Transmission Lines Formulae
- [SI-LIST] : Trusting tools.
- [SI-LIST] : Updated differential article
- [SI-LIST] : use of this List
- [SI-LIST] : Via Capacitances ...
- [SI-LIST] : viewing the output of LARGE hspice transient runs
- [SI-LIST] : VLSI'99: Xth IFIP Conference on VLSI (2nd Call)
- [SI-LIST] : VLSI'99: Xth IFIP Conference on VLSI (Final Call for Papers)
- [SI-LIST] : Vocabulary of Signal Integrity Degradations
- [SI-LIST] : voltage measurements using a current probe
- [SI-LIST] : Vote on IBIS Version 3.2 (Standards Proposal 4557)
- [SI-LIST] : w element
- [SI-LIST] : W Element Models
- [SI-LIST] : Waveform comparison metrics
- [SI-LIST] : web documentation system testing
- [SI-LIST] : What is effect of adjacent signal layer on PCB
- [SI-LIST] : What is effect of adjacent signal layer on PCB on Zo?
- [SI-LIST] : What speed scope should I consider?
- [SI-LIST] : Where can ifind data on SSTL and/or RAMBUS
- [SI-LIST] : Where can ifind data on SSTL and/or RAMBUS technology
- [SI-LIST] : Which signal integrity tool to use
- [SI-LIST] : Which witch
- [SI-LIST] : XTK vs. Spectraquest.........
- [SI-LIST] : your request
- [SI-LIST] :EMI filtering and ESD protection
- [SI-LIST]:Mixing GTLP Tx with GTL Rx
- About your SILIST comments
- Atomic animation
- AW: [SI-LIST] : Anyone interested in PCB Design Techniques for SI & EMC?
- AW: [SI-LIST] : buried capacitance vendors?
- AW: [SI-LIST] : connector substitution for high speed signals
- AW: [SI-LIST] : Effect of low Zo for unterminated lines
- AW: [SI-LIST] : Flexible and Passive PCI Backplane?
- AW: [SI-LIST] : Proposal: Rs correlation/collaboration for W-Elem
- AW: [SI-LIST] : What speed scope should I consider?
- Book for sale
- connector substitution for high speed signals
- forks & such
- FW: [SI-LIST] : A Question About Power Noise.
- FW: [SI-LIST] : Chip level Vs Board level SI
- FW: [SI-LIST] : EMC at low frequencies
- FW: [SI-LIST] : EMC quiet serial device???
- FW: [SI-LIST] : FPC impedance control
- Fw: [SI-LIST] : Looking for a sensitive Gigabit receiver part
- FW: [SI-LIST] : METASTABILITY IN FLIP FLOPS
- FW: [SI-LIST] : Oscillation in lumped circuits and transmission l
- FW: [SI-LIST] : SSTL Versus full swing PROS/CONS -- Acronyms
- Fw: [SI-LIST] : use of this List
- FW: FW: [SI-LIST] : METASTABILITY IN FLIP FLOPS
- FW: FWIW - RE: [SI-LIST] : Atomic animation
- FWIW - RE: [SI-LIST] : Atomic animation
- Message from mail server
- Q:Via Capacitance
- R:[SI-LIST] : High frequency decoupling Capacitors
- R:[SI-LIST] : Materials from MMontrose PCB Design Techniques for SI &
- R:R:[SI-LIST] : Materials from MMontrose PCB Design Techniques fo r SI
- RE : [SI-LIST] : looking for info on Hspice vs Star-Sim compariso
- RE : [SI-LIST] : looking for info on Hspice vs Star-Sim comparison
- RE: [SI-LIST] : "Damn Fast" buffer
- RE: [SI-LIST] : "Picket Fence" (Via Fence) for increasing isolati
- RE: [SI-LIST] : 1 GHz probe plans posted
- RE: [SI-LIST] : 20-H Rule for Power Planes
- RE: [SI-LIST] : 8b/10b
- RE: [SI-LIST] : [SI-LIST] Positive ECL (PECL) voltage swings, but
- RE: [SI-LIST] : A Question About Power Noise.
- RE: [SI-LIST] : About HSPICE model
- RE: [SI-LIST] : Accuracy of Hspice's W element
- RE: [SI-LIST] : Acronyms list
- RE: [SI-LIST] : Advice for long bus?
- RE: [SI-LIST] : An Interesting Presentation
- RE: [SI-LIST] : Anyone doing SI simulations for Pentium II
- RE: [SI-LIST] : Anyone doing SI simulations for Pentium II boards?
- RE: [SI-LIST] : Atomic animation
- RE: [SI-LIST] : Automatic/Semi-automatic design check of PCB layo
- RE: [SI-LIST] : Best type of models, edge rates & load
- RE: [SI-LIST] : BGA pin location
- RE: [SI-LIST] : BGA socket modeling
- RE: [SI-LIST] : BGA vs Leaded - summary
- RE: [SI-LIST] : Broadside Coupled Traces
- RE: [SI-LIST] : buried capacitance vendors?
- RE: [SI-LIST] : Call for presentations, 3-D packaging advanced te
- RE: [SI-LIST] : Capacitance in a Ceramic changes ?i usedf
- RE: [SI-LIST] : CBT for Signal Integrity
- RE: [SI-LIST] : Chip level Vs Board level SI
- RE: [SI-LIST] : Clock Skew Measurements
- RE: [SI-LIST] : coming up with average power estimates for buffer
- RE: [SI-LIST] : coming up with average power estimates for buffers
- RE: [SI-LIST] : Complex Math examples?
- RE: [SI-LIST] : connector substitution for high speed signals
- RE: [SI-LIST] : Critical Length
- RE: [SI-LIST] : Cross hatched planes
- RE: [SI-LIST] : Decoupling caps and power plane effects
- RE: [SI-LIST] : Decoupling strategy in tight spaces
- RE: [SI-LIST] : Different board vendors different impedances
- RE: [SI-LIST] : Different IBIS question
- RE: [SI-LIST] : Different oz copper for grounds
- RE: [SI-LIST] : differential pair routing
- RE: [SI-LIST] : Distinguishing Differential Models
- RE: [SI-LIST] : Double Messages....?
- RE: [SI-LIST] : Edge rates
- RE: [SI-LIST] : Effect of low Zo for unterminated lines
- RE: [SI-LIST] : even-odd mode influence
- RE: [SI-LIST] : even-odd mode influence
- RE: [SI-LIST] : Eye diagram displays from HSPICE simulations
- RE: [SI-LIST] : eye pattern definition
- RE: [SI-LIST] : Features to look for in an SI Tool
- RE: [SI-LIST] : Ferrite Bead models
- RE: [SI-LIST] : Flexible and Passive PCI Backplane?
- RE: [SI-LIST] : FPC impedance control
- RE: [SI-LIST] : FR-4 and PCB Tolerances
- RE: [SI-LIST] : Gigabit testing standards and methods wanted
- RE: [SI-LIST] : GND on the outer layers
- RE: [SI-LIST] : Ground gap problem
- RE: [SI-LIST] : Guard trace question
- RE: [SI-LIST] : High frequency decoupling Capacitors
- RE: [SI-LIST] : High signal density controlled impedance connecto
- RE: [SI-LIST] : high-power board
- RE: [SI-LIST] : How board over-shoot under-shoot influence a chip
- RE: [SI-LIST] : How do you use buried capacitance?
- RE: [SI-LIST] : How to decouple POWER/GND , heavy current backpla
- RE: [SI-LIST] : How to find a way to solute the double-side PCB d
- RE: [SI-LIST] : How to treat the ASIC package pin-assigns
- RE: [SI-LIST] : HSTL voltage levels
- RE: [SI-LIST] : Hyperlinx
- RE: [SI-LIST] : IBIS Model Libraries
- RE: [SI-LIST] : IBIS Modeling Info Requested
- RE: [SI-LIST] : Ibis models
- RE: [SI-LIST] : IBIS simulation of ZBT SRAM
- RE: [SI-LIST] : IBIS Subcommittee Formed to Review Spice to
- RE: [SI-LIST] : IBIS Subcommittee Formed to Review Spice to IBIS
- RE: [SI-LIST] : IDE bus question
- RE: [SI-LIST] : Looking for a sensitive Gigabit receiver part
- RE: [SI-LIST] : looking for signal integrity engineer position
- RE: [SI-LIST] : Looking Inside IBIS Model
- RE: [SI-LIST] : low jitter PLL ?
- RE: [SI-LIST] : LVDS-to-PECL and vice versa
- RE: [SI-LIST] : LVTTL Drivers vs. LS
- RE: [SI-LIST] : mail list subject
- RE: [SI-LIST] : Measuring noise with Differntial probe
- RE: [SI-LIST] : MG Interconnectix
- RE: [SI-LIST] : micro BGA SI vrs PCB consideration
- RE: [SI-LIST] : mini co-ax
- RE: [SI-LIST] : Missing Person
- RE: [SI-LIST] : Modification of decoupling-caps
- RE: [SI-LIST] : Mutual capacitamce and inductance
- RE: [SI-LIST] : Mutual capacitance and inductance
- RE: [SI-LIST] : Need information on inexpensive Circuit simulatio
- RE: [SI-LIST] : Noise Voltage levels vs. EMI levels
- RE: [SI-LIST] : Non-standard bus termination (2nd posting)
- RE: [SI-LIST] : Of thermal reliefs and signal integrity....
- RE: [SI-LIST] : Online crosstalk simulation [...more comments?]
- RE: [SI-LIST] : Opamp spice model
- RE: [SI-LIST] : Opportunity at Dell - Austin, TX
- RE: [SI-LIST] : Oscillation in lumped circuits and
- RE: [SI-LIST] : Oscillation in lumped circuits and transmission l
- RE: [SI-LIST] : OVERSHOOT/MAX. VOLTAGE RATING
- RE: [SI-LIST] : Package Parasitics Modelling
- RE: [SI-LIST] : Parallel tracks on Flexible PCB without Ground Pl
- RE: [SI-LIST] : Parallel tracks on Flexible PCB without Ground Plane
- RE: [SI-LIST] : PCB impedance variation v.s. layout pattern
- RE: [SI-LIST] : Power Distribution along a connector
- RE: [SI-LIST] : Power/Gnd Pin Input Impedance
- RE: [SI-LIST] : predriver control schemes (was Some Semiconductor
- RE: [SI-LIST] : Proposal: Rs correlation/collaboration for
- RE: [SI-LIST] : Proposal: Rs correlation/collaboration for W-Elem
- RE: [SI-LIST] : Proposal: Rs correlation/collaboration for W-Elem ents
- RE: [SI-LIST] : Proposal: Rs correlation/collaboration for W-Elem ents
- RE: [SI-LIST] : ps-resolution
- RE: [SI-LIST] : Q: HSPICE w-elements' RLCGs - conversion coeffici
- RE: [SI-LIST] : Q: Plane-jumping return currents
- RE: [SI-LIST] : Question about Multiple PWBA Ground
- RE: [SI-LIST] : question about timing analysis
- RE: [SI-LIST] : Rambus SI problems ...
- RE: [SI-LIST] : RE: Another decoupling question
- RE: [SI-LIST] : RE: [SI-LIST] : AMPredictor. Signal Integrity Ana
- RE: [SI-LIST] : RE: [SI-LIST]: Long bus or star?
- RE: [SI-LIST] : RE: RESULTS to Proposal: Rs correlation/collabora
- RE: [SI-LIST] : RE: RESULTS to Proposal: Rs correlation/collaboration for W-Elements
- RE: [SI-LIST] : Resistivity of IC routing
- RE: [SI-LIST] : Resonant clocks (was:coming up with average power
- RE: [SI-LIST] : response to semiconductor I/O edge rates
- RE: [SI-LIST] : return current distribution in diff pairs
- RE: [SI-LIST] : revised 1GHz probe plans
- RE: [SI-LIST] : RF & Digital
- RE: [SI-LIST] : RF Design Question
- RE: [SI-LIST] : Search ? IBIS to HSPICE Tool...
- RE: [SI-LIST] : Search for a screen capture tool
- RE: [SI-LIST] : Searching For Equations Governing Serpentine Trac
- RE: [SI-LIST] : Searching For Equations Governing Serpentine Traces
- RE: [SI-LIST] : Seeking SI models for memory DIMMs.
- RE: [SI-LIST] : Serpentine traces
- RE: [SI-LIST] : SI courses
- RE: [SI-LIST] : Signal Polarities
- RE: [SI-LIST] : signal propagation questions
- RE: [SI-LIST] : Slotted ground planes
- RE: [SI-LIST] : Slow falling edge of a signal.
- RE: [SI-LIST] : SMA connector routing
- RE: [SI-LIST] : Some Semiconductors are Unnecessarily Fast
- RE: [SI-LIST] : source for AVX small inductance caps
- RE: [SI-LIST] : Speakers sought for Conference on EMC Compliance
- RE: [SI-LIST] : Spread spectrum project
- RE: [SI-LIST] : SSTL Versus full swing PROS/CONS
- RE: [SI-LIST] : SSTL Versus full swing PROS/CONS -- Acronyms
- RE: [SI-LIST] : Stackup Extraction
- RE: [SI-LIST] : TDR measurements
- RE: [SI-LIST] : Terminating a bidirectional bus
- RE: [SI-LIST] : the old high-frequency return current model
- RE: [SI-LIST] : The overshoot and undershoot criteria in PCI spe
- RE: [SI-LIST] : Thin Power Plane Dielectrics
- RE: [SI-LIST] : Trace Capacitance
- RE: [SI-LIST] : Trace impedance measurement for dual stripline
- RE: [SI-LIST] : Traces Impedance without plane
- RE: [SI-LIST] : Traces Over Plane Clearances
- RE: [SI-LIST] : Transmission Lines Formulae
- RE: [SI-LIST] : use of this List
- RE: [SI-LIST] : Via Capacitances ...
- RE: [SI-LIST] : viewing the output of LARGE hspice transient runs
- RE: [SI-LIST] : Vocabulary of Signal Integrity Degradations
- RE: [SI-LIST] : voltage measurements using a current probe
- RE: [SI-LIST] : W-Elements
- RE: [SI-LIST] : Waveform comparison metrics
- RE: [SI-LIST] : What is effect of adjacent signal layer on PCB on
- RE: [SI-LIST] : What speed scope should I consider?
- RE: [SI-LIST] : Which signal integrity tool to use
- RE: can't seem to post- RE: [SI-LIST] : the old high-frequency return current model
- RE: FW: [SI-LIST] : FPC impedance control
- RE: R:[SI-LIST] : Materials from MMontrose PCB Design Techniques
- RE: RE: [SI-LIST] : Mutual capacitance and inductance
- Re[2]: [SI-LIST] : Parallel tracks on Flexible PCB without G
- Re[2]: [SI-LIST] : Transmission Lines Formulae
- Re[2]: [SI-LIST] : Via Capacitances ...
- SPAM
- Subject: [SI-LIST] : Power Distribution along a connector
- Tektronix IPA-510 question
- viewing the output of LARGE hspice transient runs
Last message date: Wed 20 Oct 1999 - 10:53:47 PDT
Archived on: Wed Oct 20 1999 - 11:47:41 PDT
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