Don't have any specific quantitative info, but you might try some
what-if scenarios with spice to see if you can come up with an
acceptable solution.
You might also consider increasing the size of the anti-via clearance
around the center-pin pad to reduce the capacitance to ground. Also,
if you are going through a multilayer board, if possible, make sure your
center pin isn't connected to floating "do nothing" pads in the inner layers.
(this makes the fab people nervous though:)
-Ray Anderson
Sun Microsystems Inc.
> From: "Ellis, John R" <EllisJR@bergelect.com>
> To: "'si-list@silab.Eng.Sun.COM'" <si-list@silab.eng.sun.com>
> Subject: [SI-LIST] : SMA connector routing
> Date: Thu, 18 Feb 1999 11:53:11 -0600
>
> Whenever we route to a through hole SMA connector we get abig capacitive dip
> in the via beneath the connector itself. Does anyone have any board layout
> recommendations to reduce this dip? I'm using end launch connectors
> whenever I can, but there are times when only the the thru-hole will
> suffice.
>
> John Ellis
> FCI
>
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