RE: [SI-LIST] : The overshoot and undershoot criteria in PCI spe

Ingraham, Andrew (Andrew.Ingraham@compaq.com)
Tue, 12 Oct 1999 08:18:21 -0700

Read the spec carefully. These are the thevenin equivalent voltages,
applied behind a thevenin equivalent resistance. If your chip sees such
voltages directly on its pins during this exercise, then you probably left
out the clamp diodes.

If the reliability of your chip would be adversely affected by such
waveforms, then either you shouldn't leave out the one clamp that is
optional (positive clamp in the 5V environment), or you should redesign your
chips to make them more reliable.

The theory goes that you could actually see overshoot stresses of this
magnitude in real life on a PCI bus. Maybe the pulsewidths wouldn't be so
great, but it is easy to argue that the magnitudes can be. (For example, if
a 3.3V PCI bus was quiescent at Vcc=+3.6V and the driver switches to 0V, the
voltage transient at the far end of an open-circuit transmission line could
double to reach -3.6V, behind some thevenin equivalent resistance.)

>What are the overshoot and undershoot criteria for PCI 5V and 3.3V
environment?
>Based on PCI spec. rev. 2.2, 4.2.2.3 Section, Maximum AC Ratings and
Device Protection,
>for 3.3V PCI, the criteria seems to be 7.1V for overshoot and -3.5V for
undershoot.
>
>For 5V PCI, 11V is for overshoot and -5.5V is for undershoot.
>
>I wonder that such big overshoot and undershoot voltages will affect the
reliability of chips even the voltages are within the >spec.

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