Re: [SI-LIST] : Some Semiconductors are Unnecessarily Fast

Matt (boomer@lsil.com)
Thu, 15 Jul 1999 13:31:15 -0500

This is a multi-part message in MIME format.
--------------4D37B22BCE4853C60683279B
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

hi,

The problem with the current controlled predriver approach is that
to achieve a constant current the gate voltage of the output
device needs to be almost constant (very slow) until it goes
linear vds<vgs-vt.

For a high drive cell with a low cap load (you want the bus
to look capacitive [that is the whole point of the edge rate
control]) That may be almost all the way across the output swing.

This means that your predriver current needs to be very weak
which means that the max frequency the IO can support will be
very slow if you want the predriver to go full swing (otherwise
you start to see data-dependant jitter).

plus you are assuming a process independant current source
for the predriver....

matt

"D. C. Sessions" wrote:
>
> Mike Degerstrom wrote:
> >
> > Raymond,
> >
> > I'd also like to know more about the edge-rate control with use of
> > a series resistor as has been mentioned is used with the Analog
> > Devices 21020. I have seen mention of parts that use a reference
> > resistor to control output impedance, i.e., drive strengths such
> > as in the HP article by Esch, and Manley. I also noticed that
> > IBM sells SRAMs with programmable impedance control drivers.
>
> In principal, you can control edge rates by setting the predriver
> currents. Output edge rate is mainly dictated by the risetime
> of the final driver devices' gate voltages, and that in turn is
> dictated by the Ids of the predriver transistors. If you provided
> the predriver with a bias voltage to a two-transistor stack (or
> three with tristate) such that the switching transistors just
> gated the current from the bias transistor the result would be
> a controlled dv/dt at the final drive gate and indirectly a
> controlled edge rate.
>
> Since the gate capacitance and transconductance of the final devices
> are roughly proportional with process, this approach would give
> a reasonably stable output edge rate. Of course there would be
> timing impact, and if you controlled the turnoff transistors you'd
> have crowbar current. (If you don't control them, then the turnoff
> transition could get VERY abrupt, making the net output a bit odd.)
>
> So it *could* be done, albeit with tradeoffs in power, noise, and
> layout complexity.
>
> --
> D. C. Sessions
> dc.sessions@vlsi.com
>
> **** To unsubscribe from si-list: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****
--------------4D37B22BCE4853C60683279B
Content-Type: text/x-vcard; charset=us-ascii;
name="boomer.vcf"
Content-Transfer-Encoding: 7bit
Content-Description: Card for Matt (boomer) Russell
Content-Disposition: attachment;
filename="boomer.vcf"

begin:vcard
n:Russell;Matthew
x-mozilla-html:FALSE
org:LSI LOGIC
version:2.1
email;internet:boomer@lsil.com
title:Circuit Applications
tel;fax:612-921-8479
tel;work:612-921-8307 Pager 888-860-3630
adr;quoted-printable:;;8300 Norman Center Drive=0D=0Asuite 730;Bloomington ;MN;55437;USA
x-mozilla-cpt:;2
fn:Matthew Russell
end:vcard

--------------4D37B22BCE4853C60683279B--

**** To unsubscribe from si-list: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****