... Richard Mellitz
Intel
-----Original Message-----
From: D. C. Sessions [mailto:[email protected]]
Sent: Monday, August 02, 1999 9:04 PM
To: [email protected]
Subject: [SI-LIST] : Resonant clocks (was:coming up
with average power estimates for buffers)
Dennis Tomlinson wrote:
> This reminds me of (tongue fully in cheek), a scheme put
forth by
> a cohort of mine for distributing clock in digital systems
> without suffering the ill effects of propagation delay.
Simply drive
> a 1/2 wavelength line at one extreme end with a sinusoid.
In the steady
> state, at any instant in time, all points on the line
would be of
> the same polarity - but with differing amplitudes. At any
point along
> the line where clock is needed, attach a high-Z, wide
dynamic range,
> zero crossing detector (ZCD) at the end of a zero length
stub. If all
> ZCDs have equal propagation delay, then all will derive an
identically
> time matched replica of the clock. An added bonus is the
steady state
> driver power dissipation, which would be 0;-)
>
> Time to get back to real products,
Well, you *thought* it was all in jest. Actually, resonant
clocking
schemes have occasionally been used. The lovely thing about
them is
that they are insensitive to driver output impedance (in
addition to
the very low power dissipation.)
For embedded systems with fixed clock frequencies they
actually make
a lot of sense, although unlike your proposal the most
common styles
are variations on point-to-point or star distributions.
--
D. C. Sessions
[email protected]
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