Re: [SI-LIST] : Differential clock jitter and switching noise

Chuck Hill (chuckh@altaeng.com)
Fri, 02 Apr 1999 10:38:32 -0700

Jose, DC,

At 09:31 AM 4/2/99 -0700, Jose Luis Gonzalez wrote:
>"D. C. Sessions" wrote:
>>
>> > Assuming switching noise spikes are symmetrical in power and ground
>> > on-chip
>> > lines,
>>
>> Bad assumption. Most on-chip supply noise results from IR drop
>> on the supply lines. Since a great deal of the (for instance)
>> rising edge signal current returns on the positive rail, the
>> ground paths are NOT disturbed as much as the positive rails.
>>
>
>That applies for off-chip loads. For on-chip loads, the current
>return loop comprises both, the positive and the ground rail (for
>full CMOS output swing), independently of the output switching
>direction. Also I guess that most of the on-chip supply noise
>results from dI/dt drop. So if the effective inductance from the
>external power supply or nearest decoupling capacitor to the power
>and ground internal rails is approximately the same, the dI/dt noise
>should be symmetrical in both rails.

Is it? On chip, the substrate is usually ground, and although resistive,
it seems
some return current can flow here.

The other question I have is: on chip, the power rail is metallization and
no plane exists
like in a PCB. So how much distributed capacitance to ground (substrate)
is there? And
what differences are there between the on-chip bypassing and a PCB equivalent?

Charles Hill, consultant
Alta Engineering
chuckh@altaeng.com

>
>Jose Luis Gonzalez
>
>
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