[SI-LIST] : Anyone doing SI simulations for Pentium II boards?

Kim Helliwell (khelliwe@acuson.com)
Wed, 08 Sep 1999 12:41:38 -0700

I face the following puzzle in running a signal integrity
simulation on Pentium II board. I'm using SpecctraQuest
and Signoise, in case this matters.

I have a Pentium II IBIS model (which I converted to Cadence's
.dml format). This model appears to model all the parasitics
of the Slot 1 board in a lumped manner; I presume that the
model includes parasitics up to the edge fingers. (Does anyone
know different?)

I also have a model of a Slot 1 connector in SPICE format. Quite
aside from issues of how this model is to be used (I'm trying to
get the answer to that from the supplier) is the issue of how to
include the Slot 1 connector parasitics in the simulation. At
first, I thought I could use a design link and treat the connector
as a cable connecting the main board and the Slot 1 module, but I
think that requires that I have the "board layout" of the Pentium
module. The next thought was to treat the connector as a package, but
this doesn't work since the Pentium II module is already a package
model. So I'm left with adding the connector parasitics in some
fashion to the existing Pentium II model. I just want to check
that this is in fact the correct approach, or else find out whether
I'm giving up too soon on one of the first two approaches mentioned,
or whether there's another approach I haven't considered.

I'm sure I'm not the only one facing this, so how are others
solving it?

Kim Helliwell
Senior CAE Engineer
Acuson Corporation
Phone: 650 694 5030  FAX: 650 943 7260

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