Rail-to-rail. Of course, that means that they GENERATE less noise,
and the switchpoints are less asymmetrical, but the problems remain.
If you're REALLY lucky you can get the mfg to give you real input
specs rather than bogus TTL lookalikes.
> At 12:49 PM 5/3/99 -0700, you wrote:
> >Shayle Hirschman <firstname.lastname@example.org> writes:
> >> May I add to your question what would the answer be if the FPGA and RAM are
> >> 3.3 v devices vs. 5 v devices? Would less of a voltage swing reduce the
> >> need for termination, especially, as you are asking, on the data lines?
> >> Shayle
> >These are 3.3V devices and from some simulations that one of our students is
> >doing with Hyperlynx we see that even a 3'' inch trace needs a series
> >termination to get a clean waveform at the receiver's end. We are using IBIS
> >models for the Xilinx Virtex FPGA and a Micron ZBT SRAM device.
> >Dr. Arrigo Benedetti o e-mail: email@example.com
> >Caltech, MS 136-93 < > phone: (626) 395-3695
> >Pasadena, CA 91125 / \ fax: (626) 795-8649
> >> At 09:21 AM 5/3/99 -0700, you wrote:
> >> >Dear all,
> >> >
> >> >I would like to know you opinion on this issue. I am interfacing a
> >> >state of the art FPGA with a high speed synchronous SRAM device. Since
> >> >the interface is bidirectional (the FPGA will read and write data to
> >> >the memory) I was wondering what is is the best way to terminate this
> >> >bus. My intuition is that if the data lines are not very long, then a
> >> >series termination near the FPGA end could have an effect similar to a
> >> >series termination near the memory end when the memory is driving the
> >> >bus.
> >> >
> >> >I've in the the standard SI book, and haven't found any hint on the
> >> >problem.
-- D. C. Sessions firstname.lastname@example.org
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